Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 37
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Chapter 3: Functional Description 3–7
Block Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Figure 3–4 shows the top-level block diagram for the SDI receiver.
The received data is NRZI decoded and descrambled and then presented as a
word-aligned parallel output—20 bit for HD-SDI; 10 bit for SD-SDI (refer to
Table 3–16 on page 3–41 for
rxdata
bus definition).
Figure 3–4. SDI Receiver Block Diagram
Descrambler
SDI RECEIVER
Protocol Block
Transceiver Interface Block
Transceiver Block
Aligner
LN Extract
CRC Extract
ANC Track
TRS Match
Format
GXB RX Sample
GXB Control FSM
Triple Rate Detect
rst_rx
rx_serial_refclk
enable_sd_search
enable_hd_search
enable_3g_search
sdi_reconfig_done
rst_rx
rx_serial_refclk
sdi_rx (serial data)
gxb4_cal_clk
sdi_reconfig_clk
sdi_reconfig_togxb[3:0]
sdi_gxb_powerdown
rst_rx
en_sync_switch
rx_status[10:0]
rx_trs
rx_ln[21:0]
rxdata[19:0]
rx_data_valid_out[1:0]
crc_error_c[1:0]
crc_error_y[1:0]
rx_anc_data[19:0]
rx_anc_valid[3:0]
rx_anc_error[3:0]
rx_F[1:0]
rx_H[1:0]
rx_V[1:0]
rx_AP[1:0]
xyz_valid, rx_xyz, rx_eav
rx_clk
rx_std[1:0]
rx_std_flag_hd_sdn
sdi_start_reconfig
sdi_reconfig_fromgxb[16:0]
rx_clk
rx_hd_sdi
word_valid
word[19:0]
digital_reset
analog_reset
lock_todata
lock_torefclk
rx_clockout
rx_dataout[19:0]
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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