Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 104
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4–16 Chapter 4: SDI Audio IP Cores
SDI Audio Extract MegaCore Function
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
For register interface signals, refer to Table 4–7 on page 4–7. All SDI audio cores use
the same register interface signals.
4 Asynchronous RW
Reflects the asx bit of the RATE (sampling rate) field of the audio
control packet.
6:5 Sample rate RW
Reports the X1 and X0 bits of the sample rate code from the RATE
field of the audio control packet.
7 Status valid RW
Set to
1b
when the audio control packet is present in the video
stream.
Error Status Register
3:0 Error counter RW
Counts up to 15 errors since last reset.
Write
1b
to any bit of this field to reset the entire counter to zero.
4 Ancillary CS fail RW
Indicates that an error has been detected in the ancillary packet
checksum. This bit stays set until cleared by writing
1b
to this
register.
5 Ancillary parity fail RW
Indicates that an error has been detected in at least one of the parity
fields: the ancillary packet parity bit, the audio sample parity bit (for
SD-SDI) or the AES sample parity bit (for HD-SDI). This bit stays set
until cleared by writing
1b
to this register.
6 Channel status CRC fail RW
Indicates that an error has been detected in the channel status CRC.
This bit stays set until cleared by writing
1b
to this register.
7 Audio packet ECRC fail RW
Indicates that an error has been detected in the ECRC that forms part
of the HD audio data packet. This bit stays set until cleared by writing
1b
to this register.
FIFO Status Register
6:0 FIFO fill level RO
Reports the amount of data in either the audio output FIFO or the
Avalon-ST audio FIFO when the optional Avalon-ST Audio interface is
used.
7 Overflow/Underflow RW
This register bit goes high if there is either underflow/overflow of the
audio output FIFO or the overflow of the Avalon-ST audio FIFO,
depending on the output mode used. This register always goes high
at the beginning, so you must clear the audio FIFO first for the
register to indicate underflow or overflow.
Clock Status Register
4:0 Offset RO
Returns the current status of the digital PLL used to create the output
64 × sample rate clock.
6:5 Unused — Reserved for future use.
7 74.17-MHz video clock RO
To create a 48-kHz signal synchronous to the video clock, you must
detect whether a 1 or 1/1.001 video clock rate is used. If you detect a
1/1.001 video clock rate, this field returns high.
Channel Status RAM
7:0 Channel status data WO
Read accesses within the address range 10h to 3Fh to the channel
status RAM. This field returns the 24 bytes of channel status for X
channel starting at address 10h and the 24 bytes of channel status for
Y channel starting at address 28h.
Table 4–17. SDI Audio Extract MegaCore Function Register Map (Part 2 of 2)
Bit Name Access Description
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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