Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 70
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3–40 Chapter 3: Functional Description
Signals
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Table 3–13 lists the transmitter clock signals.
rx_coreclk
Input
Receiver controller clock input. For Cyclone IV GX devices only. The
frequency of this clock must be the same as
rx_serial_refclk
.
Because of hardware constraint, the transceiver PLL and core logic
cannot share the same clock input pin if they use transceiver PLL6
and PLL7.
refclk_rate
(2)
Input
This signal is related to the
rx_video_format
signal. Detects the
received video standard. Set input to 0 for a 148.35-MHz receiver
serial reference clock. Set input to 1 for 148.5-MHz RX serial
reference clock.
gxb_tx_clkout
Output
Transmitter clock out of transceiver. This clock is the output of the
voltage-controlled oscillator (VCO) and is used as a parallel clock for
the transmitter. It connects internally to the
tx_clkout
signal of the
ALTGX or ALT2GXB megafunction.
rx_clk
Output Transceiver CDR clock.
rx_sd_oversample_clk_out
Output
67.5-MHz oversample clock output for cascading MegaCore
functions. SD-SDI only.
rx_video_format
Output
This signal is related to the
refclk_rate
signal. Indicates the
format for the received video. The
rx_video_format
value is valid
after the frame locked signal is asserted.
For more information about the video specification, refer to
Table 3–17.
Notes to Table 3–12:
(1) You must tie the
tx_serial_refclk
and
rx_serial_refclk
signals together if you generate an SDI duplex using the Stratix V or Arria V
devices.
(2) For Cyclone IV GX devices, set the
refclk_rate
according to the
rx_coreclk
frequency.
Table 3–12. Receiver Clock Signals (Part 2 of 2)
Signal Direction Description
Table 3–13. Transmitter Clock Signals
Signal Direction Description
tx_pclk
Input
Transmitter parallel clock input. For SD-SDI = 27 MHz;
for HD-SDI = 74 MHz and for 3G-SDI = 148.5 MHz.
tx_serial_refclk
(1)
Input Transceiver reference clock input. Low jitter. Refer to Table 3–5.
tx_serial_refclk1
Input
Optional port for transceiver reference clock input. Low jitter. Similar
to
tx_serial_refclk
. Only available for Arria II, Stratix IV GX, and
HardCopy IV GX devices.
Note to Table 3–13:
(1) You must tie the
tx_serial_refclk
and
rx_serial_refclk
signals together if you generate an SDI duplex using Arria V or Stratix V
devices.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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