Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 34
- Seite / 140
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
3–4 Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Table 3–1 lists the bit allocation for
txdata
.
For HD-SDI operation, the current video line number is inserted at the appropriate
point in each line. A CRC is also calculated and inserted for the luma and chroma
channels.
The parallel video data is scrambled and NRZI encoded according to the SDI
specification.
The transceiver converts the encoded parallel data into the high-speed serial output
(parallel-to-serial conversion).
HD-SDI LN Insertion
SMPTE292M section 5.4 defines the format of two words that are included in each
HD-SDI video line to indicate the current line number. The HD-SDI LN insertion
module takes the lower 11-bit
tx_ln
, and formats and inserts it as two words in the
output data. The HD-SDI LN insertion module accepts the current line number as an
input.
1 For more information about the line insertion for other video standards, refer to the
description for
tx_ln
signal in Table 3–16 on page 3–41.
The LN words (LN0 and LN1) overwrite the two words that follow the “XYZ” word
of the EAV TRS sequence. The same value is included in the luma and chroma
channels.
For correct LN insertion, you must assert the
tx_trs
signal must be asserted for the
first word of both EAV and SAV TRSs (refer to Figure 3–31 on page 3–47 and
Figure 3–32 on page 3–48).
1 If the system does not know the line number, you can implement logic to detect the
output video format and then determine the current line. This function is outside the
scope of this SDI MegaCore function.
HD-SDI CRC Generation and Insertion
SMPTE292M section 5.5 defines a CRC that is included in the chroma and luma
channels for each HD-SDI video line. The HD-SDI CRC module generates, formats,
and inserts the required CRC in the output data.
The HD-SDI CRC module identifies the words that you must include in the CRC
calculation, and also determines where you must insert the words in the output data.
The formatted CRC data words (
YCR0
and
YCR1
for the luma channel,
CCR0
and
CCR1
for the chroma channel) overwrite the two words that follow the line number words
after the EAV. A separate calculation is provided for the luma and chroma channels.
Table 3–1. Bit Allocation for txdata for Supported Video Standards
txdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B
[19:10] Unused Y Y
Cb, Y, Cr, Y
multiplex (link A)
[9:0]
Cb, Y, Cr, Y
multiplex
CC
Cb, Y, Cr, Y
multiplex (link B)
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
Verwandte Produkte und Handbücher für Messgeräte Altera Serial Digital Interface (SDI) MegaCore Function
(44 Seiten)© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.040 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern