Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 110
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4–22 Chapter 4: SDI Audio IP Cores
Avalon-ST Audio Interface
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Figure 4–6 shows the audio data and audio control packets for Avalon-ST audio
interface.
The Avalon-ST audio protocol separates the audio data from the control or status data
to facilitate audio data processing. The protocol defines that the data is packed LSB
first, which matches the AES3 data. The audio data size is configurable at compile
time and matches the audio data sample size. Including the aux, the audio data word
would be 24 bits.
In Avalon-ST audio, the data is packed as 24 bit symbols, typically with 1 symbol per
beat [23:0]. The core transmits the audio control data as a packet after the audio data
to meet the latency requirements.
The packet type identifier defines the packet type. The packet type identifier is the
first value of any packet, when the start of packet signal is high. The audio data packet
identifier is 0×A and the audio control data packet identifier is 0×E. Table 4–29 lists
the packet types.
The preamble data, XYZ from AES, describes whether the data is at the start of a block
and which channel the audio refers to. In Avalon-ST audio protocol, you are not
required to transport the preamble data because the information stored in the data is
described by the start of packet, end of packet, and channel signals.
Figure 4–6. Audio Data and Audio Control Packets for Avalon-ST Audio Interface
Note to Figure 4–6:
(1) The sequence of audio control packets begins with V bit, U bit, and finally C bit. The audio control packets for U and C bits are similar to V bits.
D0 D192
...
V0 V7
... ...
MSB
Audio Data Packet
(1)
Audio Control Packet
LSB
MSB LSB
AUX data (4 bits) Audio data (20 bits) AUX data (4 bits) Audio data (20 bits)
MSB LSB MSB LSB
1st frame
of V bit
24th frame
of V bit
192nd frame
of V bit
Table 4–29. Avalon-ST Packet Types
Type Identifier Description
0 Video data packet
1–8 User packet types
10 Audio data packet
14 Audio control data packet
15 Video control data packet
9–15 Reserved
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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