Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 9
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Chapter 1: About This MegaCore Function 1–3
General Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
General Description
The Society of Motion Picture and Television Engineers (SMPTE) have defined an SDI
that video system designers use widely as an interconnect between equipment in
video production facilities.
The SDI MegaCore function can handle the following SDI data rates:
■ 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 10-Bit
4:2:2 Component Serial Digital Interface
■ 1.5-Gbps HD-SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for
High Definition Television Systems
■ 3-Gbps SDI, as defined by SMPTE425M-AB 2006 3Gb/s Signal/Data Serial Interface–
Source Image Format Mapping
■ Preliminary support for dual link SDI, as defined by SMPTE372M-Dual Link
1.5Gb/s Digital Interface for 1920×1080 and 2048×1080 Picture Formats
Cyclone
®
Final (3)
Cyclone II (2) Final
Cyclone III (2) Final
Cyclone III LS (2) Final
Cyclone IV GX (4) Final
Cyclone V (5)
Refer to the What’s New in Altera IP page of
the Altera website.
HardCopy
®
III/ IV E HardCopy Compilation
HardCopy IV GX HardCopy Compilation
Stratix
®
(2) Final
Stratix GX Final
Stratix II (2) Final
Stratix II GX Final
Stratix III (2) Final
Stratix IV (1) Final
Stratix V (1)
Refer to the What’s New in Altera IP page of
the Altera website.
Other device families No support
Notes to Table 1–4:
(1) If you have only 27 MHz to drive the SDI MegaCore function in SD-SDI mode, you require an additional PLL to
generate a 67.5-MHz reference clock.
(2) The Cyclone series of devices, and Stratix, Stratix II, and Stratix III devices only support soft
serializer /deserializer (SERDES).
(3) Cyclone device support is limited to –6 speed grade devices.
(4) Transceiver dynamic configuration with channel reconfiguration mode is not supported for dual and triple standard
in EP4CGX110 and EP4CGX150 devices. Use transceiver dynamic reconfiguration with PLL reconfiguration mode
instead.
(5) The Cyclone V devices does not support the SDI Audio IP cores.
Table 1–4. Device Family Support (Part 2 of 2)
Device Family Support
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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