Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 11
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Chapter 1: About This MegaCore Function 1–5
General Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Table 1–6 lists the HD-SDI standard video format specification.
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
SM
megafunction) within your system.
■ Verify the functionality of your design and quickly evaluate its size and speed
with ease.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
You are required to obtain a license for the MegaCore function only when you are
completely satisfied with its functionality and performance, and want to take your
design to production.
f For more information about OpenCore Plus hardware evaluation using the SDI, refer
to “OpenCore Plus Time-Out Behavior” on page 3–39 and AN 320: OpenCore Plus
Evaluation of Megafunctions.
Table 1–6. HD-SDI Video Format Specification
(1)
(2)
SMPTE292M Video Format
Sample per
Active Line
Active Line
per Frame
Sample per
Total Line
Total Line
per Frame
Frame Rate
SDI 11.1
Support
274M 1920 x 1080 1920 1080
2200 1125 60 Yes
2640 1125 50 Yes
2200 1125 30 Yes
2640 1125 25 Yes
2750 1125 24 Yes
296M 1280 x 720 1280 720
1650 750 60 Yes
1980 750 50 Yes
3300 750 30 Yes
3960 750 25 Yes
4125 750 24 Yes
260M 1920 x 1035 1920 1035 2200 1125 30 Yes
295M 1920 x 1080 1920 1080
2376 1250 25 Yes
2376 1250 50 Yes
Notes to Table 1–6:
(1) The video formats support 4:2:2(YC’
B
C’
R
)/10-bit, 4:4:4(RGB)/(YC’
B
C’
R
), 4:4:4:4 (RGB+A)/(YC’
B
C’
R
+A)/10-bit, 4:4:4(YC’
B
C’
R
)/12-bit,
4:4:4(RGB)/12-bit, and 4:2:2 (YC’
B
C’
R
)/12-bit mapping structures.
(2) 3G-SDI is similar to HD-SDI except the data bit rate is twice that of HD-SDI or approximately 3 Gbps.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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