Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 35
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Chapter 3: Functional Description 3–5
Block Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
The CRC is calculated for all words in the active digital line, starting with the first
active word line and finishing with the final word of the line number (
LN1
). The initial
value of the CRC is set to zero, then the polynomial generator equation
CRC(X) = X
18
+X
5
+X
4
+ 1 is applied.
The HD-SDI CRC module implements the CRC calculation by iteratively applying the
polynomial generator equation to each bit of the output data, processing the LSB first.
For correct CRC generation and insertion, the
tx_trs
signal must be asserted for the
first word of both EAV and SAV TRS (refer to Figure 3–31 on page 3–47 and
Figure 3–32 on page 3–48).
Scrambling and NRZI Coding
SMPTE292M section 5 and SMPTE292M section 7 define a common channel coding
that is used for both SDI and HD-SDI. This channel coding consists of a scrambling
function (G
1
(X) = X
9
+X
4
+ 1) followed by NRZI encoding (G
2
(X) = X + 1). The
scrambling module implements this channel coding. You can configure the module to
process either 10-bit or 20-bit parallel data.
The scrambling module implements the channel coding by iteratively applying the
scrambling and NRZI encoding algorithm to each bit of the output data, processing
the LSB first. Figure C.1 of SMPTE259M shows how the algorithm is implemented.
Transceiver Clock
Figure 3–3 shows the clocking scheme for the transmitter.
The
tx_serial_refclk1
is an optional port that is enabled when you turn on the
Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration in the SDI
parameter editor.
Figure 3–3. Transmitter Clocking Scheme
Protocol Block (Transmitter) Transceiver Interface Block Transceiver Block
ALTGXB
tx_pclk
encoded_data[19:0]
txdata[19:0]
tx_pclk
pll_inclk
pll_inclk1
cal_blk_clk
reconfig_clk
gxb_txword[19:0]
gxb_tx_core_clk
tx_clkout
(optional)
gxb_tx_clkout
sdi_tx
(serial data out)
tx_pclk
tx_serial_refclk
tx_serial_refclk1
gxb2_cal_clk
sdi_reconfig_clk
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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