Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 100
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4–12 Chapter 4: SDI Audio IP Cores
SDI Audio Extract MegaCore Function
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Signals
Table 4–11 lists the clock recovery input and output signals for the SDI Audio Extract
MegaCore function.
Table 4–12 shows the video input signals for the SDI Audio Extract MegaCore
function.
Table 4–11. Clock Recovery Input and Output Signals
Signal Width Direction Description
reset
[0:0] Input This signal resets the system.
fix_clk
[0:0] Input
Assert this 200 MHz reference clock when you turn on the
Include Clock parameter.
aud_clk_out
[0:0] Output
The core asserts this 64 × sample rate clock (3.072 MHz
audio clock) when you turn on the Include Clock parameter.
You use this clock to clock the audio interface in synchronous
mode.
As the core creates this clock digitally, it is prone to higher
levels of jitter.
aud_clk48_out
[0:0] Output
The core asserts this sample rate clock when you turn on the
Include Clock parameter.
Table 4–12. Video Input Signals
Signal Width Direction Description
vid_clk
[0:0] Input
The video clock that is typically 27 MHz for SD-SDI,
74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz
or 148.35 MHz for 3G-SDI standards. You can use
higher clock rates with the
vid_datavalid
signal.
vid_std
[1:0] Input
Set this signal to
00b
to indicate 10-bit SD-SDI
formats,
01b
for 20-bit HD-SDI formats,
11b
for 3G
Level A formats, and
10b
for 3G-SDI Level B formats.
vid_datavalid
[0:0] Input Assert this signal when the video data is valid.
vid_data
[19:0] Input
This signal carries luma and chroma information.
SD-SDI:
■ [19:10] Unused
■ [9:0] Cb,Y, Cr, Y multiplex
HD-SDI and 3G-SDI Level A:
■ [19:10] Y
■ [9:0] C
3G-SDI Level B:
■ [19:10] Cb,Y, Cr, Y multiplex (link A)
■ [9:0] Cb,Y, Cr, Y multiplex (link B)
vid_locked
[0:0] Input Assert this signal when the video is locked.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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