Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 137
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February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this user guide.
Date Version Changes
February 2013 12.1
■ Updated Table 1–2, Table 1–4, Table 1–5, and Table 1–7 for version 12.1 release.
■ Updated information on duplex setting in Table 3–10.
■ Updated information on
rx_video_format
signal in Table 3–12.
■ Added a note in Table 3–13 to include information about Arria V and Stratix V devices.
■ Added Table 3–14—transceiver PHY management clock and reset signals.
■ Updated information on
rx_status
signal in Table 3–18.
■ Added data width information for
SDI_RECONFIG_TOGXB
and
SDI_RECONFIG_FROMGXB
signals in Table 3–19.
■ Updated the Starting channel number parameter description in Table 3–21.
■ Added reset sequence information and timing diagram in Figure 3–25.
November 2011 11.1
■ Added information about Arria V and Stratix V devices.
■ Updated Table 1–2, Table 1–5, Table 1–6, and Table 1–7 for version 11.1 release.
■ Updated “Parameterizing” section to include additional steps to turn on the Enable TX PLL
select for 1/1.000 and 1/1.001 data rate reconfiguration option.
■ Updated “Transmitter Clocks”, “Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX,
Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices”, Table 3–7, Table 3–9,
Figure 3–3, Figure 3–8, to include information about the optional serial reference clock
feature.
■ Updated Table 3–21 with Enable TX PLL select for 1/1.000 and 1/1.001 data rate
reconfiguration parameter.
■ Updated information in the “Transceiver Dynamic Reconfiguration for Dual Standard and
Triple Standard Receivers”.
■ Updated Table 4–1, Table 4–4, and Table 4–14 to include information about asynchronous
and synchcronous modes.
July 2011 11.0
■ Added information about accessing transceiver.
■ Updated Table 3–12 with new signals,
refclk_rate
and
rx_video_format
.
■ Updated the high-level block diagram of design example for the SDI Audio IP Core to
include AES input and output modules.
■ Updated the SDI Audio IP Core register maps.
December 2010 10.1
■ Added two new GUI parameters for SDI MegaCore function: Enable Spread Spectrum
feature and Tolerance to consecutive missed EAV.
■ Added a chapter on the SDI Audio IP Cores: SDI Audio Embed, Audio Extract, Clocked
Audio Input, and Clocked Audio Output MegaCore functions.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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