Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 74
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3–44 Chapter 3: Functional Description
Signals
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
rx_AP
[1:0] Output
This is an active picture interval timing signal. The receiver
aserts this signal when the active picture interval is active.
HD-SDI/SD-SDI: bit 1 unused; bit 0
rx_ap
Dual link: bit 1 link B unused; bit 0 link A
rx_ap
3G-SDI Level A: bit 1 unused; bit 0
rx_ap
3G-SDI Level B: bit 1 link A
rx_ap
; bit 0 link B
rx_ap
rxdata
[(20N – 1):0] Output
Receiver parallel data. SD-SDI uses 9:0; HD-SDI uses 20N
– 1:0.
SD-SDI bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex
HD-SDI bits 19:10 Y; bits 9:0 C
Dual link: bits 39:30 Y link B; bits 29:20 C link B;
bits 19:10 Y link A, bits 9:0 C link A
3G-SDI Level A: bits 19:10 Y; bits 9:0 C
3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A);
bits 9:0 Cb, Y, Cr, Y multiplex (link B)
rx_data_valid_out
[1:0] Output
Data valid from the oversampling logic. Asserted to
indicate current data on
rxdata
is valid.
Bit 0 of this bus indicates valid data on
rxdata
. When
receiving SMPTE 425M-B signals in 3G-SDI or triple
standard, bit 1 indicates that data on
rxdata
is from
virtual link A; bit 0 indicates the data is from virtual link B.
Refer to Figure 3–34 and Figure 3–35, and SMPTE425M-B
2006 3Gb/s Signal/Data Serial Interface – Source Image
Format Mapping.
rx_F
[1:0] Output
This is a field bit timing signal. This signal indicates which
video field is currently active. For interlaced frame, 0
means first field (F0) while 1 means second field (F1). For
progressive frame, the value is always 0.
HD-SDI/SD: bit 1 unused; bit 0
rx_f
Dual link: bit 1 unused; bit 0
rx_f
3G-SDI Level A: bit 1:0 unused
3G-SDI Level B: bit 1:0 unused
rx_H
[1:0] Output
This is a horizontal blanking interval timing signal. The
receiver asserts this signal when the horizontal blanking
interval is active.
HD-SDI/SD-SDI: bit 1 unused; bit 0
rx_h
Dual link: bit 1 unused; bit 0
rx_h
3G-SDI Level A: bit 1 unused; bit 0
rx_h
3G-SDI Level B: bit 1 link A
rx_h
; bit 0 link B
rx_h
Table 3–16. Interface Signals (Part 4 of 5)
Signal Width Direction Description
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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