Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 78
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3–48 Chapter 3: Functional Description
Signals
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Figure 3–32. Behavior of tx_std, tx_trs, and tx_ln Signals—425MB
tx_pclk
EAV
SAV
EAV
tx_trs
txdata[19:10]
txdata[9:0]
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
3FF(C) 3FF(Y) 000(C)
10
000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
tx_std[1:0]
tx_ln[21:11]
tx_ln[10:0]
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C) XYZ(Y)
11’d2
11’d3
11’d4
11’d1
Figure 3–33. Behavior of crc_error_y and crc_error_c Signals
(1)
Notes to Figure 3–33:
(1) When a CRC error occurs, the
crc_error_y
or
crc_error_c
signal goes high until the next line. For HD, Dual Link, and 3G Level A, only
crc_error_y[0]
and
crc_error_c[0]
signals are used. For 3G Level B,
crc_error_y[0]
and
crc_error_c[0]
signals are used for link B,
and
crc_error_y[1]
and
crc_error_c[1]
signals are used for link A.
(2) The CRC error signals are asserted after the CRC data checked, when the
rx_H
signal is high. A high CRC signal indicates that there is error in the
previous line data. In this case, both Y and C have CRC error.
(3) The CRC error signals are deasserted on the next line after the CRC data is checked.
rx_clk
rxdata[19:0]
crc_error_c
rxdata[9:0]
rx_V
rx_H
rx_ln
crc_error_y
000
000
000
3FF XYZ CRC1
CRC2
LN1
LN2
XYZ CRC1 CRC2
LN1
LN2
000
3FF
000001a
000 000
000
3FF XYZ CRC1 CRC2
LN1
LN2
XYZ CRC1 CRC2
LN1
LN2
000
3FF
000001b
(2) (3)
Figure 3–34. Behavior of rx_data_valid Signal—425MA
Figure 3–35. Behavior of rx_data_valid Signal—425MB
rx_clk (148.5 MHz)
rxdata[19:10]
rxdata[9:0]
rx_data_valid_out[0]
rx_data_valid_out[1]
3FF(Y) 000(Y) 000(Y) XYZ(Y)000(Y)
3FF(C) 000(C) 000(C) XYZ(C)000(C)
rx_clk (148.5 MHz)
rxdata[19:10]
rxdata[9:0]
rx_data_valid_out[0]
rx_data_valid_out[1]
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C)000(Y)
3FF(C) 3FF(Y) 000(C) 000(Y) 000(C) 000(Y) XYZ(C)000(Y)
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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