Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 44
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3–14 Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
For SD-SDI operation, you can derive the transmitter reference clock from
pclk
by
using one of the Stratix GX PLLs. The PLL can multiply the 27-MHz
pclk
signal by
5/2.
For dual standard operation, use an external multiplexer to select between the SD-SDI
and HD-SDI reference clock.
The Stratix GX architecture allows each group of four transmitters (a transceiver
quad) to have a separate transmitter reference clock.
Table 3–5 lists frequencies of the transmitter clock,
tx_serial_refclk
, for Stratix GX
devices.
Figure 3–8 shows the transmitter clocks for different video standards.
Table 3–5. Transmitter Clock Frequency—Stratix GX Devices
Video Standard
(1)
Clock Frequency (MHz)
SD-SDI 67.5
HD-SDI (including dual link) 74.175/74.25
(2)
HD-SDI with two times oversample 148.35/148.5
(2)
Dual standard 67.5/74.175/74.25
(2)
Notes to Table 3–5:
(1) Stratix GX devices do not support 3G and triple standard modes.
(2) The
tx_serial_refclk
signal must be externally multiplexed.
Figure 3–8. Transmitter Clocks—Stratix GX Devices
Notes to Figure 3–8:
(1) This frequency can be either 74.175 or 74.25 MHz, to support 1.4835 or 1.485 Gbps HD-SDI respectively.
(2) The multiplexer must not be in the device.
SDI MegaCore
Function
74.XX MHz (
1
)
from reference clock
Serial Data
HD-SDI
SDI MegaCore
Function
67.5 MHz
from PLL or Pin
Serial Data
SD-SDI
SDI MegaCore
Function
67.5 MHz
74.XX MHz (
1
)
Serial Data
(
2
)
Dual Standard
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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