Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 71
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Chapter 3: Functional Description 3–41
Signals
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Table 3–14 lists the transceiver PHY management clock and reset signals.
Table 3–15 lists the soft transceiver clock signals.
Table 3–16 lists the interface signals.
Table 3–14. Transceiver PHY Management Signals
(1)
Signal Direction Description
phy_mgmt_clk
Input
Avalon-MM clock input for the transceiver PHY management
interface. Use the same clock for the PHY management interface and
transceiver reconfiguration. The frequency range is 100-125 MHz to
meet the specification of the transceiver reconfiguration clock.
phy_mgmt_clk_reset
Input
Reset signal for the transceiver PHY management interface. This
signal is active high and level sensitive. This signal can be tied to the
same reset port as
tx_rst
or
rx_rst
signal in simplex mode.
In duplex mode, this reset signal acts as a global reset for both the
transmitter and receiver. If you require a different reset for the
transmitter and receiver, separate this signal from the
tx_rst
and
rx_rst
signal.
Note to Table 3–14:
(1) The transceiver PHY management clock and reset signals are available for Stratix V and Arria V devices only.
Table 3–15. Soft Transceiver Clock Signals
Signal Direction Description
rx_sd_refclk_337
Input Soft transceiver 337.5-MHz sampling clock.
rx_sd_refclk_337_90deg
Input Soft transceiver 337.5-MHz sampling clock with 90
°
phase shift.
rx_sd_refclk_135
Input Soft transceiver 135-MHz parallel clock for receiver.
tx_sd_refclk_270
Input Soft transceiver 270-MHz parallel clock for transmitter.
Table 3–16. Interface Signals (Part 1 of 5)
Signal Width Direction Description
enable_crc
[(N – 1):0] Input Enables CRC insertion for HD-SDI and 3G-SDI.
enable_hd_search
1 Input
Enables search for HD-SDI signal in dual or triple standard
mode.
enable_sd_search
1 Input
Enables search for SD-SDI signal in dual or triple standard
mode.
enable_3g_search
1 Input Enables search for 3G-SDI signal in triple standard mode.
enable_ln
[(N – 1):0] Input
Enables line number insertion for HD-SDI and 3G-SDI
modes.
en_sync_switch
1 Input
Enables aligner and format blocks to realign immediately
so that the downstream is completely non-disruptive.
rst_rx
1 Input
Reset signal, which holds the receiver in reset. It must be
synchronous to
rx_serial_refclk
clock domain for the
receiver. Issues a reset to the SDI MegaCore function after
power-up to ensure reliable operation. Refer to
Figure 3–29.
For HD-SDI dual link receiver, assert this signal when both
link A and link B are ready for the first time.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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