Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 39
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Chapter 3: Functional Description 3–9
Block Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Video Timing Flags Extraction
The TRS match module extracts the F, V, and H video timing flags from the received
data. You can use these flags for receiver format detection, or in the implementation of
a flywheel function.
The TRS match module also identifies the line number and CRC words for HD-SDI.
RP168 Switching Compliance
To meet the RP168 requirements, the transceiver must be able to recover by the end of
the switching line. Table 3–4 lists the supported video switching type.
f For more information about the switching line and time for different video formats,
refer to RP168.
Figure 3–5 and Figure 3–6 show the behaviors of the aligner and format blocks during
the RP168 switching.
The aligner block immediately aligns to the next TRS timing based on the user input
en_sync_switch
signal.
Table 3–4. Supported Video Switching Type
Standard/ Data Rate Format RP168 Support Switching Source
Fixed Switch (same format) Yes HD-1080i30 to HD-1080i30
Fixed Switch No HD-1080 to HD-720
Switch Fixed No HD-1080 to SD-525
Switch Switch No HD-1080 to SD-525
Figure 3–5. Aligner Block Behavior
Notes to Figure 3–5:
(1) Mismatch in alignment.
(2) New alignment on the next TRS.
(3) Data aligned to new alignment.
(4) Zero interrupt.
tx_data
dead_time
(1)
switch
line
10200
10200
00000H
00000H
40020H 10200H
10200H 10200H
10200H
10200H
10200H
10200H
10200H
10200H
10 11 12
12H03H
alignment
align_locked/rx_status[2]
rx_data
(2)
(2)
(4)
(3)
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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