Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 42
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3–12 Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Transceiver Clock
Figure 3–7 shows the general clocking scheme for the receiver.
Transceiver—Soft-Logic Implementation
The soft-logic implementation differs for the transmitter and the receiver.
Transmitter
For the transmitter, in the soft-logic transceiver a 10-bit parallel word is converted into
a serial data output format. A 10-bit shift register loaded at the word rate from the
encoder and unloaded at the bit rate of the LVDS output buffer is implemented for
that function. A PLL that multiplies a 27-MHz reference clock by ten provides the
bit-rate clock and enables jitter-controlled SDI transmit serialization.
Transmitter Clocks
The serializer requires a 270-MHz clock, which you can generate from an external
source (
tx_sd_refclk_270
).
The 27-MHz parallel video clock (
tx_pclk
) samples and processes the parallel video
input.
Transmitter Clock Multiplexer Option
This is a new feature introduced in version 11.1. The transmitter block has the option
of receiving an additional reference clock to allow dynamic switching between the
1/1000 and 1/1.001 data rates. This feature is available in Arria II, Stratix IV, and
HardCopy IV devices.
By default, you can use the
tx_serial_refclk
for any normal SDI operations and the
tx_serial_refclk1
as an additional clock input parameter. You can then switch to the
clock source selected by using the transceiver dynamic reconfiguration.
Figure 3–7. Receiver Clocking Scheme
Protocol Block (Receiver) Transceiver Interface Block Transceiver Block
ALTGXB
rxclk
rxword[19:0]
rxdata[19:0]
rx_refclk rx_cruclk
cal_blk_clk
reconfig_clk
gxb_rxword[19:0] rx_dataout[19:0]
gxb_refclk rxclk
rx_clkout
rxclk
rx_serial_refclk
gxb2_cal_clk
sdi_reconfig_clk
sdi_rx
(serial data in)
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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