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© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Additional Information
Revision History
The following table shows the revision history for this user guide.
How to Contact Altera
For the most up-to-date information about Altera products, refer to the following table.
Date and
Document
Version Changes Made Summary of Changes
November 2009
v9.1
Maintenance release and obsolescence notification Maintenance release and
obsolescence notification
March 2009
v9.0
Maintenance release Maintenance release
November 2008
v8.1
Maintenance release Maintenance release
May 2008
v8.0
Updated the MegaCore IP version, and incorporated the following
modifications:
■ Updated Table 3–12 to clarify behavior of some read-only registers
■ Described Quartus II IP File (.qip)
■ Fixed Features to clarify that this MegaCore function supports
low-swing differential signaling with 100-ohm differential impedance
Maintenance release and
minor text updates
October 2007
v7.2
Maintenance release —
May 2007
v7.1
Maintenance release; updated release information —
December 2006
v7.0
Maintenance release —
December 2006
6.1
In Chapter 2, updated the MegaCore IP version, and incorporated the
following documentation errata:
■ Setting Virtual Pin Attributes Recommended
■ Enabling Clock Latency Recommended for All Variations
—
October 2005
v1.4.0
Added Stratix
®
II GX support —
February 2004
v1.3.0 rev 1
Added support for Altera
®
Stratix II devices, IP functional simulation
models, and the OpenCore Plus evaluation feature
—
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email [email protected]
Product literature Website www.altera.com/literature
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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