Altera HyperTransport MegaCore Function Bedienungsanleitung Seite 42
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3–16 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
1 The following description distinguishes between an HT packet and an Atlantic
packet. An HT packet is defined as indicated in the HT specification with various
types including 32-bit commands, 64-bit commands, or various size data packets. An
Atlantic packet, however, contains one or two HT packets. An Atlantic packet can
contain only a single HT command packet (32- or 64-bit), or a single HT command
packet followed by its associated HT data packet.
HT Link Rx Signals
The HT link Rx signals are differential pair signals. Table 3–2 defines a single signal
name for each pair, and the same is true of the HyperTransport MegaCore port
declarations. These signals must be assigned the HyperTransport I/O standard in the
Quartus II software; the software creates the differential pair automatically during
compilation.
HT Link System Signals
Table 3–3 describes the HT link system signals. These signals are 2.5-V tolerant
LVCMOS. The HyperTransport MegaCore function does not implement the optional
HT power management signals, LDTSTOP# and LDTREQ#.
HT Link Tx Signals
The HT link Tx signals are differential pair signals. Table 3–4 defines a single signal
name for each pair, and the same is true of the HyperTransport MegaCore port
declarations. These signals must be assigned the HyperTransport I/O standard in the
Quartus II software; the software creates the differential pair automatically during
compilation.
Table 3–2. HT Link Rx Signals
Signal Name Direction Description
RxClk_i Input RxClk_i is the received HT clock and is used to clock the RxCAD_i and RxCTL_i
inputs.
RxCAD_i[7:0] Input RxCAD_i[7:0] is the received HT command, address, and data bus.
RxCTL_i Input RxCTL_i is the received HT control signal.
Table 3–3. HT Link System Signals
Signal Name Direction Description
Rstn Input Rstn is the HT Reset# signal. HT allows it to be a wired OR signal with multiple drivers,
however, the HyperTransport MegaCore function treats it as input only.
PwrOk Input PwrOk is the HT power okay signal. HT allows it to be a wired OR signal with multiple drivers,
however, the HyperTransport MegaCore treats it as input only.
Table 3–4. HT Link Tx Signals
Signal Name Direction Description
TxClk_o Output TxClk_o is the transmitted HT clock and is center-aligned with respect to the
TxCAD_o[7:0] and TxCTL_o signals.
TxCAD_o[7:0] Output TxCAD_o[7:0] is the transmitted HT command, address, and data bus.
TxCTL_o Output TxCTL_o is the transmitted HT control signal.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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