Altera HyperTransport MegaCore Function Bedienungsanleitung Seite 22
- Seite / 76
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
2–14 Chapter 2: Getting Started
Program a Device
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
5. Set the I/O Standard to HyperTransport for the I/O pins that are connected to the
HyperTransport wrapper ports TxCAD_o[7:0], TxCTL_o, TxClk_o,
RxCAD_i[7:0], RxCTL_i, and RxClk_i, by performing the following steps:
a. In the row for the pin, double-click in the Assignment Name column.
b. In the Assignment Name list, click I/O Standard.
c. In the row for the pin, double-click in the Val ue column.
d. In the Value list, click HyperTransport.
6. Set the I/O Standard to 2.5 V for the I/O pins connected to the HyperTransport
wrapper ports PwrOk and Rstn.
7. If you are compiling the HyperTransport MegaCore function variation file
top-level entity in your Quartus II project, set virtual pin attributes for all of the
internal interface signals of the variation.
1 An example Quartus II project that has all of the above I/O standards set,
and virtual pin and clock latency settings, is included with the
HyperTransport MegaCore function installation. Refer to “Example
Quartus II Project” on page 2–16.
8. Turn on the Quartus II timing analysis setting Enable Clock Latency to perform
correct timing analysis. Refer to Quartus II Help for instructions on how to make
this assignment.
9. Set the remaining constraints in the Quartus II software, including the device, pin
assignments, timing requirements, and any other relevant constraints. Refer to
Appendix B, Stratix Device Pin Assignments for more details about assigning
pins. If you have not made pin assignments for your board design, you can use the
Quartus II software to automatically assign pins.
10. On the Processing menu, click Start Compilation to compile the design.
Program a Device
After you compile your design, you can program your targeted Altera device and
verify your design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the
HyperTransport MegaCore function before you purchase a license. OpenCore Plus
evaluation allows you to generate an IP functional simulation model and produce a
time-limited programming file.
You can simulate the HyperTransport MegaCore function in your design and perform
a time-limited evaluation of your design in hardware.
1 For more information about OpenCore Plus hardware evaluation for the
HyperTransport MegaCore function, refer to “OpenCore Plus Time-Out Behavior” on
page 3–40 and AN320: OpenCore Plus Evaluation of Megafunctions.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
Verwandte Produkte und Handbücher für Messgeräte Altera HyperTransport MegaCore Function
Messgeräte Altera MAX II Bedienungsanleitung
(38 Seiten)
(38 Seiten)
Messgeräte Altera MAX V CPLD Bedienungsanleitung
(30 Seiten)
(30 Seiten)
Messgeräte Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung
(196 Seiten)
(196 Seiten)
Messgeräte Altera JNEye Bedienungsanleitung
(194 Seiten)
(194 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Bedienungsanleitung
(413 Seiten)
(413 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI4-St Bedienungsanleitung
(231 Seiten)
(231 Seiten)
Messgeräte Altera Nios II Bedienungsanleitung
(22 Seiten)
(22 Seiten)
Messgeräte Altera Nios II Bedienungsanleitung
(22 Seiten)
(22 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Bedienungsanleitung
(783 Seiten)
(783 Seiten)
Messgeräte Altera PCI Development Kit, Cyclone II Edition Getting St Bedienungsanleitung
(40 Seiten)
(40 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.052 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern