Altera HyperTransport MegaCore Function Bedienungsanleitung Seite 58
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3–32 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Table 3–13 shows the format of the primary interface capabilities block. The block is
located at the address specified in the Capabilities Pointer field in the CSR map shown
in Table 3–12.
The following sections explain the entries in Table 3–12 and Table 3–13.
HT Device Header
The following sections describe the HT device header.
Vendor ID, Device ID (Offset 0x00)
Vendor ID and device ID are read-only, as defined in the PCI specification. They are
parameters in the HyperTransport MegaCore function.
PCI Command Register (Offset 0x04)
Table 3–14 describes the PCI command register.
Table 3–13. Primary Interface Capabilities Block Format
HyperTransport Slave/Primary Interface Capabilities Block Format
Address Byte 3 Byte 2 Byte1 Byte 0
+00 Command (1) Capabilities Pointer (2) Capabilities ID (2)
+04 Link Config 0 (1) Link Control 0 (1)
+08 Link Config 1 (1) Link Control 1 (1)
+0C Link Frequency Cap 0 (2) Link Error 0
(1)
Link Freq 0 (1) Revision ID (2)
+10 Link Frequency Cap 1 (2) Link Error 1
(1)
Link Freq 1 (1) Feature (1)
+14 Error Handling (1) Enumeration Scratch Pad (4)
+18 Reserved (3) Mem Limit Upper (4) Mem Base Upper (4)
Notes to Table 3–13:
(1) The register is read/write in the HyperTransport MegaCore function.
(2) The register is a read-only register in the HyperTransport MegaCore function.
(3) The configuration register is not used by the HT specification. The register is a read-only register, and Read returns 0s.
(4) The register is not supported in the HyperTransport MegaCore function. The register is a read-only register and Read returns 0s.
Table 3–14. PCI Command Register (Offset 0x04) (Part 1 of 2)
Bits Name
Register
Type
Reset
Used Description
0 I/O Space Enable R/W Warm Must be set for the device to claim non-compatibility accesses to I/O
address space
1 Memory Space
Enable
R/W Warm Must be set for the device to claim non-compatibility accesses to memory
address space.
2 Bus Master Enable R/W Warm Must be set for the device to issue memory or I/O requests onto the HT
chain.
7:3 Reserved
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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