Altera HyperTransport MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 18)

2–10 Chapter 2: Getting Started

MegaCore Function Walkthrough

HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation

2. Turn on Generate Simulation Model, as shown in Figure 2–10.

3. Select the language in the Language list. In this case, Verilo g H D L was chosen.

If you are synthesizing your design with a third-party EDA synthesis tool, you can

generate a netlist for the synthesis tool to estimate timing and resource usage for this

megafunction.

1. To generate a netlist, turn on Generate netlist.

2. Click OK.

Figure 2–9. Set Up Simulation

Figure 2–10. Generate Simulation Model

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 75 76

User Guide 1
UG-MCHYPRTRNS-1.12 2
Contents 3
Appendix C. Example Design 4
Additional Information 4
Release Information 5
Device Family Support 5
Introduction 6
Features 6
Performance 7
Notes to Table 1–4: 8
Notes to Table 1–5: 8
2. Getting Started 9
MegaCore Function Walkthrough 10
Step 1: Parameterize 13
Step 2: Set Up Simulation 17
Figure 2–9. Set Up Simulation 18
Step 3: Generate 19
Notes to Table 2–1: 20
Compile the Design 21
Simulate the Design 21
Program a Device 22
Set Up Licensing 23
Example Quartus II Project 24
■ input_ht_vector.dat 25
■ output_ht_vector.dat 25
■ input_ui_vector.dat 25
■ output_ui_vector.dat 25
About the Test Vectors 26
3. Specifications 27
HT Systems 28
HT Flow Control 29
Physical Interface 30
Protocol Interface 31
End-Chain Handler 32
Rx Claimed Buffers 32
Tx Buffers 32
Scheduler 32
Clocking Options 33
Shared Rx/Tx Clock 34
Shared Ref/Tx Clock 34
Chapter 3: Specifications 3–9 35
Preliminary 35
Shared Rx/Tx/Ref Clock 36
Note to Figure 3–8: 37
HT Link Rx Signals 42
HT Link System Signals 42
HT Link Tx Signals 42
Notes to Table 3–6: 45
Notes to Figure 3–10: 46
Notes to Figure 3–11: 46
Notes to Figure 3–12: 47
Notes to Figure 3–13: 47
Notes to Table 3–8: 51
Addr[39:8] 52
Notes to Figure 3–16: 53
Notes to Figure 3–17: 53
Notes to Figure 3–18: 54
User Interface System Signals 55
Using PLL Resets 55
CSR Interface Signals 56
CSR Module 57
Notes to Table 3–13: 58
Notes: to Table 3–16: 60
A. Parameters 67
Base Address Registers 68
Advanced Settings 69
A–4 Appendix A: Parameters 70
Parameter Lists 70
Guidelines 71
C. Example Design 73
General Description 74
Typographic Conventions 76

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