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3–4 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Physical Interface
The physical interface module contains the logic that interfaces the HyperTransport
MegaCore function to the physical link signals. It contains the logic for both the
receiver and transmitter portions. The SERDES functionality is embedded into the
Altera device to ensure operation at maximum speed.
Rx Deserialization Logic and Clock Generation
This module receives serial data from each RxCTL_i and RxCAD_i bit and converts it
to a parallel data stream. The Rx clock generator (implemented in a fast PLL)
multiplies the receiver Rx link RxClk_i by two to capture RxCTL_i and RxCAD_i.
The data is then deserialized by a factor of eight and clocked by a divided-by-four
clock for use in the synchronization and alignment layer.
Tx Serialization Logic and Clock Generation
This module transmits serial data on the link interface. Data is transferred from the
internal module in parallel and is serialized on the link interface. The data entering
this module is already split into channels. The serialization circuit drives TxCAD_o
and TxCTL_o. The Tx clock generator multiplies the Tx alignment logic clock by eight
to serialize the TxCTL_o and TxCAD_o signals, and generates a multiplied-by-four
clock for use as the HT TxClk_o.
Synchronization and Alignment
The synchronization and alignment layer is responsible for synchronizing clock
domains and aligning data to the natural boundaries.
Figure 3–3. HyperTransport MegaCore Function Block Diagram
TxPHY
Rx Alignment
Tx Alignment
Rx
Claimed
Buffers
Rx Packet
Processor
Tx Packet
Buffering
End-
Chain
Handler
Tx Packet
Scheduling
&
Framing
Protocol InterfaceSynch & AlignmentPhysical Interface
Reset Generation
RxPHY
Tx Clock
Generation
RxClk_i
RxCAD_i[7:0]
RxCTL_i
TxClk_o
TxCAD_o[7:0]
TxCTL_o
Rstn
PwrOk
C
S
R
Rx
Interface
Tx &Rx
Buffer Credit
Counters
CSR
Interface
Rx
Sync
FIFO
Tx
Interface
Tx
Sync
FIFO
Rx Response Req/Data
Rx Posted Req/Data
Rx Non-Posted Req/Data
Tx Response Req/Data
Tx Posted Req/Data
Tx Non-Posted Req/Data
Rx Clock
Generation
×2
÷4
Rx Link Clock Divided by 4
×8
×4
Ref Clk
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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