Altera HyperTransport MegaCore Function Bedienungsanleitung Seite 63
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Chapter 3: Specifications 3–37
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Link Error Registers (Actual Offsets 0x4D, 0x51)
There are two registers of this type, one for each link. In the HyperTransport
MegaCore function, register 0 defines the link connected to the host bridge. For
end-chain applications, only register zero is used. Table 3–19 describes the HT
capability link error registers.
Link Frequency Capability Registers (Actual Offsets 0x4E, 0x52)
Each link frequency capability register is a 16-bit read only register that indicates the
frequency capability of the link. Two registers are defined, one for each link. For
end-chain applications, only register 0 is used. Table 3–20 and Table 3–21 describe the
link frequency registers.
Table 3–19. HT Capability Link Error 0 Register Offset: Capability Pointer + 0x0D (Actual Offset: 0x4D)
Bits Name
Register
Type Default Reset Used Description
3:0 Link Frequency
Register
R/W 0 Cold Intended to control the frequency of the link transmit clock,
but has no effect in the HyperTransport MegaCore function.
4 Protocol Error R/C 0 Cold Indicates that a protocol error was detected. The
HyperTransport MegaCore function reports a protocol error
when the RxCTL_i signal changes on other than a 4-byte
boundary.
5 Over Flow Error R/C 0 Cold Indicates that a packet was received but there was no room
in the Rx packet buffer. Indicates a failure in the flow
control mechanism.
6 End of Chain Error R/C 0 Cold Indicates a posted request of response has been given to
this transmitter when it is an end chain.
7 CTL Timeout R/W 0 Warm Indicates how long CTL may be low before a device
indicates a protocol error. 0 indicates one millisecond; 1
indicates 1 second.
Table 3–20. HT Capability Link Frequency 0 Capability Register Bits Offset Capability Pointer + 0x0E (Actual Offset: 0x4E)
Bits Name
Register
Type Default
Reset
Used Description
15:0 Supported
Frequencies
R/O See Table 3–21. N/A Indicates the supported frequencies of operation. The
default value is set based on the HT_RX_CLK_PERIOD
Parameter.
Table 3–21. Link Frequency 0 Capability Register Default Value
HT_RX_CLK_PERIOD
Register
Value Supported Frequencies (MHz)
5000 0x0001 200
3333 0x0003 200, 300
2500 0x0007 200, 300, 400
2000 0x000F 200, 300, 400, 500
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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