Altera HyperTransport MegaCore Function Bedienungsanleitung Seite 7
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Chapter 1: About this MegaCore Function 1–3
Performance
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
■ 32-bit and 64-bit support across all base address registers (BARs)
■ Automatically handles all CSR space accesses
■ Verilog HDL and VHDL simulation support
OpenCore Plus Evaluation
With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
™
megafunction) within your system
■ Verify the functionality of your design, as well as quickly and easily evaluate its
size and speed
■ Generate time-limited device programming files for designs that include
MegaCore functions
■ Program a device and verify your design in hardware
You only need to purchase a license for the MegaCore function when you are
completely satisfied with its functionality and performance, and want to take your
design to production.
f For more information about OpenCore Plus hardware evaluation using the
HyperTransport MegaCore function, refer to “OpenCore Plus Time-Out Behavior” on
page 3–40 and AN 320: OpenCore Plus Evaluation of Megafunctions.
Performance
The HyperTransport MegaCore function uses 20 differential I/O pin pairs and 2
single-ended I/O pins, requiring 42 pins total. Table 1–3 through Table 1–5 show
typical performance and adaptive look-up table (ALUT) or logic element (LE) usage
for the HyperTransport MegaCore function in StratixIIGX, StratixII, Stratix, and
Stratix GX devices respectively, using the Quartus
®
II software version 7.1.
Table 1–3 shows the maximum supported data rates in megabits per second (Mbps)
by device family and speed grade.
Table 1–3. Maximum Supported HyperTransport Data Rates (Note 1)
Device Family
Speed Grade
-3 -4 -5 -6 -7 -8
Stratix II GX devices 1000 Mbps 1000 Mbps 800 Mbps N/A (2) N/A (2) N/A (2)
Stratix II devices 1000 Mbps 1000 Mbps 800 Mbps N/A (2) N/A (2) N/A (2)
Stratix devices
(Flip-Chip packages)
N/A (2) N/A (2) 800 Mbps 800 Mbps 600 Mbps 400 Mbps
Stratix devices
(Wire Bond packages)
N/A (2) N/A (2) N/A (2) 600 Mbps 400 Mbps 400 Mbps
Stratix GX devices N/A (2) N/A (2) 800 Mbps 800 Mbps 600 Mbps N/A (2)
Notes to Table 1–3:
(1) Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit interface.
(2) Devices of this speed grade are not offered in this device family.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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