Altera HyperTransport MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 35)

Chapter 3: Specifications 3–9

HyperTransport MegaCore Function Specification

Preliminary

The design must meet the following clock frequency requirements when using the

Shared Ref/Tx Clock option:

■ The frequency of RefClk must be greater than or equal to RxLnkClkD4.

■ When RefClk and RxLnkClkD4 are nominally equal but are derived from

different RxLnkClkD4, RefClk must be no more than 2,000 ppm slower than

RxLnkClkD4.

■ RefClk should run at 50, 75, 100, or 125 MHz to create the allowed HT clock

frequencies of 200, 300, 400, or 500 MHz.

1 Failing to meet these requirements results in system failure due to Tx sync FIFO buffer

underflow or Rx sync FIFO buffer overflow.

Additionally, the attached HT device may require its incoming HT link clock to be less

than or equal to its outgoing HT link clock. This requirement—along with the above

requirements—forces the RefClk frequency to be within 2,000 ppm of the

RxLnkClkD4 frequency.

1 This clocking option may not be strictly compliant with the HT specification. If

RefClk runs at a frequency other than 50 MHz, TxLnkClk does not run at the

required 200 MHz upon reset. However, in many embedded applications it may be

acceptable for the TxLnkClk to operate at 300, 400, or 500 MHz upon reset.

Depending on the time base of the supplied RefClk, the Shared Ref/Tx Clock option

implements an asynchronous or synchronous HT implementation. The time base for

the RefClk can be asynchronous or synchronous with the attached receiver’s time

base.

In most designs, you would not connect RxLnkClkD4 to anything external to the

HyperTransport MegaCore function, but it is provided for monitoring purposes if

needed.

Figure 3–6. Shared Ref/Tx Clock Option

RxClk_i

Alignment

Logic

Sync

FIFO

RefClk

Phy Synch & Alignment Protocol Interface

Protocol

Interface

Logic

SerDes

RxLnkClkD4

TxClk_o

PLL

SerDes

PLL

÷4

Alignment

Logic

×2

×4

×8

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