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Chapter 3: Specifications 3–3
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
HT Flow Control
All commands and data are separated into one of three separate virtual channels,
which provide higher performance and allow certain types of requests to pass others
to avoid deadlocks. However, in some cases, requests in one channel cannot pass
those in other channels to preserve ordering as required by systems. The three virtual
channels are:
■ Non-Posted Requests—Requests that require a response (all read requests and
optionally write requests)
■ Posted Requests—Requests that do not require a response (typically write requests)
■ Responses—Responses to non-posted requests (read responses or target done
responses to non-posted writes)
The HT flow control mechanism is a credit-based scheme maintained per virtual
channel for an individual link. A transmitter consumes a buffer credit each time it
transmits a packet and cannot transmit a packet to the receiver unless a buffer credit is
available. The receiver provides buffer credits for each available buffer at link
initialization, and it provides an additional buffer credit each time a buffer is freed
thereafter.
Buffer credits are transmitted in the opposite direction of the data flow as part of NOP
packets.
HyperTransport MegaCore Function Specification
This section describes the functionality and features of the 8-bit end-chain
HyperTransport MegaCore function. Figure 3–3 shows the block diagram of the
HyperTransport MegaCore function. The HyperTransport MegaCore function is
partitioned into three layers:
■ Physical Interface
■ Synchronization and Alignment
■ Protocol Interface
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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