Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 92
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5–46 Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
The
ctl_wlat
signal is only valid when the calibration has been successfully
completed by the ALTMEMPHY sequencer and does not change at any point during
normal user mode operation. Figure 5–23 shows the operation of
ctl_wlat
port.
For a half-rate design
ctl_cs_n
is 2 bits, not 1. Also the
ctl_dqs_burst
and
ctl_wdata_valid
waveforms indicate a half-rate design. This write results in a burst
of 8 at the DDR. Where
ctl_cs_n
is driven 2'
b01
, the LSB (1) is the first value driven
out of
mem_cs_n
, and the MSB (0) follows on the next
mem_clk
. Similarly, for
ctl_dqs_burst
, the LSB is driven out of
mem_dqs
first (0), then a 1 follows on the next
clock cycle. This sequence produces the continuous DQS pulse as required. Finally,
the
ctl_addr
bus is twice
MEM_IF_ADDR_WIDTH
bits wide and so the address is
concatenated to result in an address phase two
mem_clk
cycles wide.
Partial Write Operations
As part of the DDR and DDR2 SDRAM memory specifications, you have the option
for partial write operations by asserting the DM pins for part of the write signal.
For designs targeting the Stratix III device families, deassert the
ctl_wdata_valid
signal during partial writes, when the write data is invalid, to save power by not
driving the DQ outputs.
For designs targeting other device families, use only the DM pins if you require
partial writes. Assert the
ctl_dqs_burst
and
ctl_wdata_valid
signals as for full write
operations, so that the DQ and DQS pins are driven during partial writes.
The I/O difference between Stratix III device families and other device families makes
it only possible to use the
ctl_dqs_burst
signal for the DQS enable in Stratix III
devices.
Using a Custom Controller with the TimeQuest Timing Analyzer
The Report DDR command in the TimeQuest Timing Analyzer may return the
message
Nothing to report
when you use a custom controller.
To avoid this situation, you can edit your project’s QSF file and set the value of the
following line to On:
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME
Alternatively, you can perform the following procedure in the Quatrus II software
GUI:
1. On the Assignments menu, click Settings.
2. In the Category list, click Compilation Process Settings.
Figure 5–23. Timing for ctl_dqs_burst, ctl_wdata_valid, Address, and Command—Half-Rate
Design
ctl_clk
ctl_addr
ctl_cs_n
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
AdAdAdAd
0101
10 1111
ctl_wlat = 2
1 2
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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