Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 109
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Chapter 6: Functional Description—High-Performance Controller II 6–15
Top-Level Signals Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
local_autopch_req
Input
User control of autoprecharge. If you turn on Enable Auto-Precharge
Control, the
local_autopch_req
signal becomes available and you can
request the controller to issue an autoprecharge write or autoprecharge read
command.
These commands cause the memory to issue a precharge command to the
current bank at the appropriate time without an explicit precharge command
from the controller. This feature is particularly useful if you know the current
read or write is the last one you intend to issue to the currently open row. The
next time you need to use that bank, the access could be quicker as the
controller does not need to precharge the bank before activating the row you
wish to access.
Upon receipt of the
local_autopch_req
signal, the controller evaluates the
pending commands in the command buffer and determines the most efficient
autoprecharge operation to perform, reordering commands if necessary.
local_self_rfsh_chip
Input
Controls which chip to issue the user refresh to. The IP core uses this active
high signal with
local_self_rfsh_req
. This signal is as wide as the
memory chip select. This signal asserts a high value to each bit that
represents the refresh for the corresponding memory chip.
For example: If
local_self_rfsh_chip
signal is assigned with a value of
4’b0101
, the controller refreshes the memory chips 0 and 2, and memory
chips 1 and 3 are not refreshed.
local_self_rfsh_req
Input
User control of the self-refresh feature. If you turn on Enable Self-Refresh
Controls, you can request that the controller place the memory devices into a
self-refresh state by asserting this signal. The controller places the memory
in the self-refresh state as soon as it can without violating the relevant timing
parameters and responds by asserting
local_self_rfsh_ack
. You can
hold the memory in the self-refresh state by keeping this signal asserted. You
can release the memory from the self-refresh state at any time by deasserting
local_self_rfsh_req
and the controller responds by deasserting
local__self_rfsh_ack
when it has successfully brought the memory out
of the self-refresh state.
local_init_done
Output
When the memory initialization, training, and calibration are complete, the
PHY sequencer asserts
ctrl_usr_mode_rdy
to the memory controller,
which then asserts this signal to indicate that the memory interface is ready
for use.
The controller still accepts read and write requests before
local_init_done
is asserted, however it does not issue them to the
memory until it is safe to do so.
This signal does not indicate that the calibration is successful.
local_rdata[]
Output
Read data bus. The width of
local_rdata
is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
local_rdata_error
Output
Asserted if the current read data has an error. This signal is only available if
you turn on Enable Error Detection and Correction Logic. The controller
asserts this signal with the
local_rdata_valid
signal.
If the controller encounters double-bit errors, no correction is made and the
controller asserts this signal.
local_rdata_valid
Output
Read data valid signal. The
local_rdata_valid
signal indicates that valid
data is present on the read data bus.
Table 6–7. Local Interface Signals (Part 3 of 4)
Signal Name Direction Description
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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