Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 108
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6–14 Chapter 6: Functional Description—High-Performance Controller II
Top-Level Signals Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
local_burstbegin
Input
The Avalon burst begin strobe, which indicates the beginning of an Avalon
burst. Unlike all other Avalon-MM signals, the burst begin signal does not
stay asserted if
local_ready
is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even if the
slave deasserts
local_ready
. The IP core samples this signal at the rising
edge of
phy_clk
when
local_write_req
is asserted. After the slave
deasserts the
local_ready
signal, the master keeps all the write request
signals asserted until
local_ready
signal becomes high again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and
local_address
from which the data should be read
is given to the memory. After the slave deasserts
local_ready
(
waitrequest_n
in Avalon interface), the master keeps all the read request
signals asserted until
local_ready
becomes high again.
local_read_req
Input
Read request signal. You cannot assert read request and write request
signals at the same time. The controller must deassert
reset_phy_clk_n
before you can assert
local_autopch_req
.
local_refresh_req
Input
User-controlled refresh request. If Enable User Auto-Refresh Controls
option is turned on,
local_refresh_req
becomes available and you are
responsible for issuing sufficient refresh requests to meet the memory
requirements. This option allows complete control over when refreshes are
issued to the memory including grouping together multiple refresh
commands. Refresh requests take priority over read and write requests,
unless the IP core is already processing the requests.
local_refresh_chip
Input
Controls which chip to issue the user refresh to. The IP core uses this active
high signal with
local_refresh_req
. This signal is as wide as the memory
chip select. This signal asserts a high value to each bit that represents the
refresh for the corresponding memory chip.
For example: If
local_refresh_chip
signal is assigned with a value of
4’b0101
, the controller refreshes the memory chips 0 and 2, and memory
chips 1 and 3 are not refreshed.
local_size[]
Input
Controls the number of beats in the requested read or write access to
memory, encoded as a binary number. The IP core supports Avalon burst
lengths from 1 to 64. The IP core derives the width of this signal based on the
burst count that you specify in the Local Maximum Burst Count option. With
the derived width, you specify a value ranging from 1 to the local maximum
burst count specified.
local_wdata[]
Input
Write data bus. The width of
local_wdata
is twice that of the memory data
bus for a full-rate controller; four times the memory data bus for a half-rate
controller.
local_write_req
Input
Write request signal. You cannot assert read request and write request signal
at the same time. The controller must deassert
reset_phy_clk_n
before
you can assert
local_write_req
.
Table 6–7. Local Interface Signals (Part 2 of 4)
Signal Name Direction Description
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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