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5–24 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Stratix III and Stratix IV Devices
Stratix IV and Stratix III devices support half-rate or full-rate DDR/DDR2 SDRAM.
The Stratix IV and Stratix III read datapath (Figure 5–8) consists of two main blocks:
■ Data capture, resynchronization, and demultiplexing
■ Read datapath logic (read datapath)
Data Capture, Resynchronization, and Demultiplexing
In Stratix IV and Stratix III devices, the smart interface module in the IOE performs
the following tasks:
■ Captures the data
■ Resynchronizes the captured data from the DQS domain to the resynchronization
clock (
resync_clk_1x
) domain
■ Converts the resynchronized data into half-rate data, which is performed by
feeding the resynchronized data into the HDR conversion block within the IOE,
which is clocked by the half-rate version of the resynchronization clock. The
resync_clk_1x
signal is generated from the I/O clock divider module based on
the
resync_clk_2x
signal from the PLL.
f For more information about IOE registers, refer to the External Memory Interfaces in
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook and the
External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV
Device Handbook.
Figure 5–8. DDR/DDR2 SDRAM Data Capture and Read Data Mapping in Stratix IV and Stratix III Devices
Note to Figure 5–8:
(1) This figure shows a half-rate variation. For a full-rate controller,
dio_radata2_1x
and
dio_rdata3_1x
are unconnected.
Dual Port RAM
Read Datapath
Data Capture, Resynchronization,
and Data Demultiplexing
mem_dq
dio_rdata3_1x
IOE
mem_dqs
mem_dqsn
dio_rdata2_1x
dio_rdata1_1x
dio_rdata0_1x
resync_clk_1x
4n bits
wr_data
wr_clk
rd_data
rd_clk
ctl_rdata
ram_rdata_1x[4n]
phy_clk_1x
Data
Mapping
Logic
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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