Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 120
- Seite / 140
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
6–26 Chapter 6: Functional Description—High-Performance Controller II
Register Maps
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
0x123
3:0 t
RCD
— Read write
The activate to read or write a timing
parameter. The range of legal values is 2-11
cycles.
7:4 t
RRD
— Read write
The activate to activate a timing parameter.
The range of legal values is 2-8 cycles.
11:8 t
RP
— Read write
The precharge to activate a timing parameter.
The range of legal values is 2-11 cycles.
15:12 t
MRD
— Read write
The mode register load time parameter. This
value is not used by the controller, as the
controller derives the correct value from the
memory type setting.
23:16 t
RAS
— Read write
The activate to precharge a timing parameter.
The range of legal values is 4-29 cycles.
31:24 t
RC
— Read write
The activate to activate a timing parameter.
The range of legal values is 8-40 cycles.
0x124
3:0 t
WTR
— Read write
The write to read a timing parameter. The
range of legal values is 1-10 cycles.
7:4 t
RTP
— Read write
The read to precharge a timing parameter.
The range of legal values is 2-8 cycles.
15:8 t
FAW
— Read write
The four-activate window timing parameter.
The range of legal values is 6-32 cycles.
31:16 Reserved. 0 — Reserved for future use.
0x125
15:0 t
REFI
— Read write
The refresh interval timing parameter. The
range of legal values is 780-6240 cycles.
23:16 t
RFC
— Read write
The refresh cycle timing parameter. The
range of legal values is 12-88 cycles.
31:24 Reserved. 0 — Reserved for future use.
0x126
3:0 CAS latency, t
CL
— Read write
This value must be set to match the memory
CAS latency. You must set this value in the
0x04 register map as well.
7:4 Additive latency, AL
Additive latency setting. The default value for
these bits is set in the Memory additive CAS
latency setting in the Preset Editor dialog
box. You must set this value in the 0x05
register map as well.
11:8 CAS write latency, CWL
CAS write latency setting. You must set this
value in the 0x06 register map as well.
15:12 Write recovery, t
WR
This value must be set to match the memory
write recovery time (t
WR
). You must set this
value in the 0x04 register map as well.
19:16 Burst Length — Read write Value must match memory burst length.
31:20 Reserved. 0 — Reserved for future use.
Table 6–15. Controller Register Map (Part 3 of 5)
Address Bit Name Default Access Description
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
Verwandte Produkte und Handbücher für Messgeräte Altera DDR SDRAM High-Performance Controllers and ALTMEMP
(157 Seiten)© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.030 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern