Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 107
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Chapter 6: Functional Description—High-Performance Controller II 6–13
Top-Level Signals Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 6–7. Local Interface Signals (Part 1 of 4)
Signal Name Direction Description
local_address[]
Input
Memory address at which the burst should start.
By default, the IP core maps local address to the bank interleaving scheme.
You can change the ordering via the Local-to-Memory Address Mapping
option in the Controller Settings page.
The IP core sizes the width of this bus according to the following equations:
■ Full rate controllers
For one chip select: width = row bits + bank bits + column bits – 1
For multiple chip selects: width = chip bits + row bits + bank bits + column
bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, the local address is 24 bits wide. To map
local_address
to bank, row
and column address:
local_address
is 24 bits wide
local_address[23:11]
= row address
[12:0]
local_address[10:9]
= bank address
[1:0]
local_address [8:0]
= column address
[9:1]
The IP core ignores the least significant bit (LSB) of the column address
(multiples of four) on the memory side, because the local data width is twice
that of the memory data bus width.
■ Half rate controllers
For one chip select: width = row bits + bank bits + column bits – 2
For multiple chip selects: width = chip bits + row bits + bank bits + column
bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, the local address is 23 bits wide. To map
local_address
to bank, row
and column address:
local_address
is 23 bits wide
local_address[22:10]
= row address
[12:0]
local_address[9:8]
= bank address
[1:0]
local_address [7:0]
= column address
[9:2]
The IP core ignores two LSBs of the column address on the memory side,
because the local data width is four times that of the memory data bus width.
local_be[]
Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be
is active high;
mem_dm
is active low.
To map
local_wdata
and
local_be
to
mem_dq
and
mem_dm
, consider a
full-rate design with 32-bit
local_wdata
and 16-bit
mem_dq
.
Local_wdata
=
< 22334455 >< 667788AA >< BBCCDDEE >
Local_be
=
< 1100 >< 0110 >< 1010 >
These values map to:
Mem_dq
=
<4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm
=
<11><00><01><10><01><01>
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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