Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 76
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5–30 Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Read Data Interface
ctl_doing_rd
Input
MEM_IF_DQS_WIDTH
×
DWIDTH_RATIO
/ 2
Doing read input. Indicates that the DDR or DDR2
SDRAM controller is currently performing a read
operation.
The controller generates
ctl_doing_rd
to the
ALTMEMPHY megafunction. The
ctl_doing_rd
signal is asserted for one
phy_clk
cycle for every
read command it issues. If there are two read
commands,
ctl_doing_rd
is asserted for two
phy_clk
cycles. The
ctl_doing_rd
signal also
enables the capture registers and generates the
ctl_mem_rdata_valid
signal. The
ctl_doing_rd
signal should be issued at the same time the read
command is sent to the ALTMEMPHY megafunction.
ctl_rdata
Output
DWIDTH_RATIO
×
MEM_IF_DWIDTH
Read data from the PHY to the controller.
ctl_rdata_valid
Output
DWIDTH_RATIO
/2
Read data valid indicating valid read data on
ctl_rdata
. This signal is two-bits wide (as only
half-rate or
DWIDTH_RATIO
= 4 is supported) to allow
controllers to issue reads and writes that are aligned
to either the half-cycle of the half-rate clock.
ctl_rlat
Output
READ_LAT_WIDTH
Contains the number of clock cycles between the
assertion of
ctl_doing_rd
and the return of valid
read data (
ctl_rdata
). This is unused by the Altera
high-performance controllers do not use
ctl_rlat
.
Address and Command Interface
ctl_addr
Input
MEM_IF_ROWADDR_WIDTH
×
DWIDTH_RATIO
/ 2
Row address from the controller.
ctl_ba
Input
MEM_IF_BANKADDR_WIDT
H
×
DWIDTH_RATIO
/ 2
Bank address from the controller.
ctl_cke
Input
MEM_IF_CS_WIDTH
×
DWIDTH_RATIO
/ 2
Clock enable from the controller.
ctl_cs_n
Input
MEM_IF_CS_WIDTH
×
DWIDTH_RATIO
/ 2
Chip select from the controller.
ctl_odt
Input
MEM_IF_CS_WIDTH
×
DWIDTH_RATIO
/ 2
On-die-termination control from the controller.
ctl_ras_n
Input
DWIDTH_RATIO
/ 2 Row address strobe signal from the controller.
ctl_we_n
Input
DWIDTH_RATIO
/ 2 Write enable.
ctl_cas_n
Input
DWIDTH_RATIO
/ 2 Column address strobe signal from the controller.
ctl_rst_n
Input
DWIDTH_RATIO
/ 2 Reset from the controller.
Calibration Control and Status Interface
ctl_mem_clk_disable
Input
MEM_IF_CLK_PAIR_
COUNT
When asserted,
mem_clk
and
mem_clk_n
are
disabled. Not supported for Cyclone III devices.
ctl_cal_success
Output 1 A
1
indicates that calibration was successful.
ctl_cal_fail
Output 1 A
1
indicates that calibration has failed.
Table 5–6. AFI Signals (Part 3 of 4)
Signal Name Type Width (1) Description
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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