Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 115
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Chapter 6: Functional Description—High-Performance Controller II 6–21
Example Top-Level File
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
■ Low-power mode operation
The example driver requests the controller to place the memory into power-down
and self-refresh states, and hold it in those states for the amount of time specified
by the
COUNTER_VALUE
signal. You can vary this value to adjust the duration the
memory is kept in the low-power states. This test is only available if your
controller variation enables the low-power mode option.
The example driver has four outputs that allow you to observe which tests are
currently running and if the tests are passing. The pass not fail (
pnf
) signal goes low
once one or more errors occur and remains low. The pass not fail per byte
(
pnf_per_byte
) signal goes low when there is incorrect data in a byte but goes back
high again once correct data is observed in the following byte. The
test_status
signal
indicates the test that is currently running, allowing you to determine which test has
failed. The
test_complete
signal goes high for a single clock cycle at the end of the set
of tests.
Table 6–11 shows the bit mapping for each test status.
Table 6–12 shows the ALTMEMPHY Debug interface signals, which are located in
<variation_name>_phy.v/vhd file.
Table 6–11. Test Status[] Bit Mapping
Bit Test
0 Sequential address test
1 Incomplete write test
2 Data mask pin test
3 Address pin test
4 Power-down test
5 Self-refresh test
6 Auto-precharge test
Table 6–12. ALTMEMPHY Debug Interface Signals
Signal Name Direction Description
d/jointfilesconvert/1708784/bg_clk
Input Debug interface clock
d/jointfilesconvert/1708784/bg_addr
Input Debug interface address
d/jointfilesconvert/1708784/bg_cs
Input Debug interface chip select
d/jointfilesconvert/1708784/bg_wr
Input Debug interface write request
d/jointfilesconvert/1708784/bg_wr_data
Input Debug interface write data
d/jointfilesconvert/1708784/bg_rd
Input Debug interface read request
d/jointfilesconvert/1708784/bg_rd_data
Input Debug interface read data
d/jointfilesconvert/1708784/bg_waitrequest
Output Debug interface wait request
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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