Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 57
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Chapter 5: Functional Description—ALTMEMPHY 5–11
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
PLL Reconfiguration
The ALTMEMPHY parameter editor automatically generates the PLL reconfiguration
block by instantiating an ALTPLL_RECONFIG variation for Stratix II and
Stratix II GX devices to match the generated ALTPLL megafunction instance. The
ALTPLL_RECONFIG megafunction varies the resynchronization clock phase and the
measure clock phase.
1 The ALTMEMPHY parameter editor does not instantiate an ALTPLL_RECONFIG
megafunction for Arria II GX devices, as this device uses the dedicated phase
stepping I/O on the PLL.
DLL
A DLL instance is included in the generated ALTMEMPHY variation. When using the
DQS to capture the DQ read data, the DLL center-aligns the DQS strobe to the DQ
data. The DLL settings depend on the interface clock frequency.
f For more information, refer to the External Memory Interfaces chapter in the device
handbook for your target device family.
Reset Management
The reset management block is responsible for the following:
■ Provides appropriately timed resets to the ALTMEMPHY megafunction datapaths
and functional modules
■ Performs the reset sequencing required for different clock domains
■ Provides reset management of PLL and PLL reconfiguration functions
Half-rate
and full
rate
measure_clk_2x
C5 Calibrated Full-Rate Global Regional
This clock is for VT
tracking. This
free-running clock
measures relative phase
shifts between the
internal clock(s) and
those being fed back
through a mimic path.
As a result, the
ALTMEMPHY
megafunction can track
VT effects on the FPGA
and compensate for the
effects.
Note to Table 5–2:
(1) In full-rate designs, a
_1x
clock may run at full-rate clock rate.
(2) The default clock network type is Global, however you can specify a regional clock network to improve clock jitter if your design uses any three
quadrants.
Table 5–2. DDR/DDR2 SDRAM Clocking in Arria II GX Devices (Part 3 of 3)
Design
Rate
Clock Name (1)
Postscale
Counter
Phase
(Degrees)
Clock
Rate
Clock Network Type
Notes
All
Quadrants
Any 3
Quadrants
(2)
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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