Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 91
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Chapter 5: Functional Description—ALTMEMPHY 5–45
Using a Custom Controller
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
■ Generation of
ctl_rdata_valid
■ Dynamic termination (Rt) control timing
The read latency,
ctl_rlat
, is advertised back to the controller. This signal indicates
how long it takes in
ctl_clk
clock cycles from assertion of the
ctl_doing_read
signal
to valid read data returning on
ctl_rdata
. The
ctl_rlat
signal is only valid when
calibration has successfully completed and never changes values during normal user
mode operation.
The ALTMEMPHY provides a signal,
ctl_rdata_valid
, to indicate that the data on
read data bus is valid. The width of this signal varies between half-rate and full-rate
designs to support the option to indicate that the read data is not word aligned.
Figure 5–21 and Figure 5–22 show these relationships.
Handshake Mechanism Between Write Commands and Write Data
In the AFI, the ALTMEMPHY output
ctl_wlat
gives the number of
ctl_clk
cycles
between the write command that is issued
ctl_cs_n
asserted and
ctl_dqs_burst
asserted. The
ctl_wlat
signal takes account of the following actions to provide a
single value in
ctl_clk
clock cycles:
■ CAS write latency
■ Additive latency
■ Datapath latencies and relative phases
■ Board layout
■ Address and command path latency and
1T
register setting, which is dynamically
setup to take into account any leveling effects
Figure 5–21. Address and Command and Read-Path Timing—Full-Rate Design
Figure 5–22. Second Read Alignment—Half-Rate Design
ctl_clk
ctl_addr
ctl_cs_n
ctl_doing_read
mem_dqs
mem_dq
ctl_rdata_valid
ctl_rdata
ctl_rlat = 9
1 2 3 4 5 6 7 8 9
ctl_clk
1 2 3 4 5 6 7
8 9
ctl_rlat = 9
ctl_addr
ctl_cs_n
ctl_doing_read
mem_dqs
mem_dq
ctl_rdata_valid
ctl_rdata
A XA
1010
10 0101
10 0101
DX XD
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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