Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung Seite 111
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Chapter 6: Functional Description—High-Performance Controller II 6–17
Sequence of Operations
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 6–9 shows the CSR interface signals.
Sequence of Operations
This section explains how the various blocks pass information in common situations.
Write Command
When a requesting master issues a write command together with write data, the
following events occur:
■ The input interface accepts the write command and the write data.
■ The input interface passes the write command to the command generator and the
write data to the write data buffer.
■ The command generator processes the command and sends it to the timing bank
pool.
■ Once all timing requirements are met and a write-data-ready notification has been
received from the write data buffer, the timing bank pool sends the command to
the arbiter.
■ When rank timing requirements are met, the arbiter grants the command request
from the timing bank pool and passes the write command to the AFI interface.
mem_err_out_n
(1) Input
Signal sent from the DIMM to the PHY to indicate that a parity error has
occured for a particular cycle. DDR3 SDRAM only.
Notes to Table 6–8:
(1) This signal is for registered DIMMs only.
Table 6–8. Interface Signals (Part 2 of 2)
Signal Name Direction Description
Table 6–9. CSR Interface Signals
Signal Name Direction Description
csr_addr[]
Input Register map address.The width of
csr_addr
is 16 bits.
csr_be[]
Input
Byte-enable signal, which you use to mask off individual bytes during writes.
csr_be
is active high.
csr_wdata[]
Input Write data bus. The width of
csr_wdata
is 32 bits.
csr_write_req
Input
Write request signal. You cannot assert
csr_write_req
and
csr_read_req
signals at the same time.
csr_read_req
Input
Read request signal. You cannot assert
csr_read_req
and
csr_write_req
signals at the same time.
csr_rdata[]
Output Read data bus. The width of
csr_rdata
is 32 bits.
csr_rdata_valid
Output
Read data valid signal. The
csr_rdata_valid
signal indicates that valid data
is present on the read data bus.
csr_waitrequest
Output
The
csr_waitrequest
signal indicates that the HPC II is busy and not ready
to accept request signals. If the
csr_waitrequest
signal goes high in the
clock cycle when a read or write request is asserted, that request is not
accepted. If the
csr_waitrequest
signal goes low, the HPC II is then ready
to accept more requests.
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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