Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 89
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Byte Offset
Register Dir Description
14'h3C10 cfg_prm_cmd[15:0]
O Base/Primary Command register for the PCI
Configuration Space.
14'h3C14 cfg_root_ctrl[7:0]
O Root control and status register of the PCI-Express
capability. This register is only available in Root
Port mode.
14'h3C18 cfg_sec_ctrl[15:0]
O Secondary bus Control and Status register of the
PCI-Express capability. This register is only
available in Root Port mode.
14'h3C1C cfg_secbus[7:0]
O Secondary bus number. Available in Root Port
mode.
14'h3C20 cfg_subbus[7:0]
O Subordinate bus number. Available in Root Port
mode.
14'h3C24 cfg_msi_addr_low[31:0]
O cfg_msi_add[31:0] is the MSI message address.
14'h3C28 cfg_msi_addr_hi[63:32]
O cfg_msi_add[63:32] is the MSI upper message
address.
14'h3C2C cfg_io_bas[19:0]
O The IO base register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C30 cfg_io_lim[19:0]
O The IO limit register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C34 cfg_np_bas[11:0]
O The non-prefetchable memory base register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C38 cfg_np_lim[11:0]
O The non-prefetchable memory limit register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C3C cfg_pr_bas_low[31:0]
O The lower 32 bits of the prefetchable base register of
the Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C40 cfg_pr_bas_hi[43:32]
O The upper 12 bits of the prefetchable base registers
of the Type1 Configuration Space. This register is
only available in Root Port mode.
UG-01145_avmm
2015.05.14
Control Register Access (CRA) Avalon-MM Slave Port
6-23
Registers
Altera Corporation
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- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
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