Altera Arria V Hard IP for PCI Express Bedienungsanleitung

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01105-1.5 User GuideArria V Hard IP for PCI ExpressDocument last updated for Altera Complete D

1–2 Chapter 1: DatasheetFeaturesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide Qsys support using the Avalon Memory-Mappe

7–2 Chapter 7: IP Core InterfacesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide1 When you are parameterizing your IP core,

Chapter 7: IP Core Interfaces 7–3Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideArria V Har

7–4 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideAvalon-ST Pa

Chapter 7: IP Core Interfaces 7–5Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide.1 The PCI E

7–6 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guiderx_st_valid

Chapter 7: IP Core Interfaces 7–7Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guiderx_st_bar8Oc

7–8 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidef For more i

Chapter 7: IP Core Interfaces 7–9Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–5 i

7–10 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 7–7

Chapter 7: IP Core Interfaces 7–11Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–9

Chapter 1: Datasheet 1–3FeaturesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidef The purpose of the Arria V Hard IP for PC

7–12 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 7–11

Chapter 7: IP Core Interfaces 7–13Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–13

7–14 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 7–15

Chapter 7: IP Core Interfaces 7–15Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideAvalon-ST T

7–16 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidetx_st_valid

Chapter 7: IP Core Interfaces 7–17Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidetx_cred_fch

7–18 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideData Alignm

Chapter 7: IP Core Interfaces 7–19Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–19

7–20 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideData Alignm

Chapter 7: IP Core Interfaces 7–21Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–24

1–4 Chapter 1: DatasheetRelease InformationArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideRelease InformationTable 1–2 prov

7–22 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 7–26

Chapter 7: IP Core Interfaces 7–23Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTo ensure p

7–24 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideReset Signa

Chapter 7: IP Core Interfaces 7–25Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidepld_clk_inu

7–26 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 7–28

Chapter 7: IP Core Interfaces 7–27Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideECC Error S

7–28 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideInterrupts

Chapter 7: IP Core Interfaces 7–29Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTable 7–10.

7–30 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidef For a des

Chapter 7: IP Core Interfaces 7–31Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidetl_cfg_sts[

Chapter 1: Datasheet 1–5Debug FeaturesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 1–1 shows a PCI Express link be

7–32 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTable 7–12

Chapter 7: IP Core Interfaces 7–33Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideConfigurati

7–34 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideConfigurati

Chapter 7: IP Core Interfaces 7–35Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidecfg_slot_ct

7–36 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidecfg_io_lim2

Chapter 7: IP Core Interfaces 7–37Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidef Refer to

7–38 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideLMI Signals

Chapter 7: IP Core Interfaces 7–39Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTable 7–16

7–40 Chapter 7: IP Core InterfacesArria V Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuidePower Manag

Chapter 7: IP Core Interfaces 7–41Arria V Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTable 7–18

1–6 Chapter 1: DatasheetIP Core VerificationArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideIP Core VerificationTo ensure co

7–42 Chapter 7: IP Core InterfacesAvalon-MM Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideAvalon-MM

Chapter 7: IP Core Interfaces 7–43Avalon-MM Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 7–

7–44 Chapter 7: IP Core InterfacesAvalon-MM Hard IP for PCI ExpressArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidef Variati

Chapter 7: IP Core Interfaces 7–45Avalon-MM Hard IP for PCI ExpressDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideRX Avalon

7–46 Chapter 7: IP Core InterfacesPhysical Layer Interface SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTable 7–23

Chapter 7: IP Core Interfaces 7–47Physical Layer Interface SignalsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTransceive

7–48 Chapter 7: IP Core InterfacesPhysical Layer Interface SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideArria V de

Chapter 7: IP Core Interfaces 7–49Physical Layer Interface SignalsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideChannel ut

7–50 Chapter 7: IP Core InterfacesPhysical Layer Interface SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide1 In all f

Chapter 7: IP Core Interfaces 7–51Physical Layer Interface SignalsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide1 In all f

Chapter 1: Datasheet 1–7Recommended Speed GradesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideSoft calibration of the tran

7–52 Chapter 7: IP Core InterfacesPhysical Layer Interface SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidetxdetectrx

Chapter 7: IP Core Interfaces 7–53Physical Layer Interface SignalsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidetxcompl0(1

7–54 Chapter 7: IP Core InterfacesPhysical Layer Interface SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guideltssmstate

Chapter 7: IP Core Interfaces 7–55Test SignalsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTest SignalsThe test_in bus pr

7–56 Chapter 7: IP Core InterfacesTest SignalsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidelane_act[3:0]OLane Active Mode

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide8. Register DescriptionsThis section describes registers that you can access

8–2 Chapter 8: Register DescriptionsConfiguration Space Register ContentArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTabl

Chapter 8: Register Descriptions 8–3Configuration Space Register ContentDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTabl

8–4 Chapter 8: Register DescriptionsConfiguration Space Register ContentArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTabl

Chapter 8: Register Descriptions 8–5Altera-Defined Vendor Specific Extended Capability (VSEC)December 2013 Altera Corporation Arria V Hard IP for PCI

1–8 Chapter 1: DatasheetRecommended Speed GradesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide

8–6 Chapter 8: Register DescriptionsAltera-Defined Vendor Specific Extended Capability (VSEC)Arria V Hard IP for PCI Express December 2013 Altera Corp

Chapter 8: Register Descriptions 8–7Altera-Defined Vendor Specific Extended Capability (VSEC)December 2013 Altera Corporation Arria V Hard IP for PCI

8–8 Chapter 8: Register DescriptionsAltera-Defined Vendor Specific Extended Capability (VSEC)Arria V Hard IP for PCI Express December 2013 Altera Corp

Chapter 8: Register Descriptions 8–9Altera-Defined Vendor Specific Extended Capability (VSEC)December 2013 Altera Corporation Arria V Hard IP for PCI

8–10 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–11PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

8–12 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–13PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

8–14 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–15PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide2. Getting Started with the Arria Hard IPfor PCI ExpressGetting Started wit

8–16 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–17PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

8–18 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–19PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

8–20 Chapter 8: Register DescriptionsPCI Express Avalon-MM Bridge Control Register Access ContentArria V Hard IP for PCI Express December 2013 Altera

Chapter 8: Register Descriptions 8–21PCI Express Avalon-MM Bridge Control Register Access ContentDecember 2013 Altera Corporation Arria V Hard IP for

8–22 Chapter 8: Register DescriptionsCorrespondence between Configuration Space Registers and the PCIe Spec 2.1Arria V Hard IP for PCI Express Decembe

Chapter 8: Register Descriptions 8–23Correspondence between Configuration Space Registers and the PCIe Spec 2.1December 2013 Altera Corporation Arria

8–24 Chapter 8: Register DescriptionsCorrespondence between Configuration Space Registers and the PCIe Spec 2.1Arria V Hard IP for PCI Express Decembe

Chapter 8: Register Descriptions 8–25Correspondence between Configuration Space Registers and the PCIe Spec 2.1December 2013 Altera Corporation Arria

2–2 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressGetting Started with the Arria Hard IP for PCI ExpressArria V Hard IP for PCI Exp

8–26 Chapter 8: Register DescriptionsCorrespondence between Configuration Space Registers and the PCIe Spec 2.1Arria V Hard IP for PCI Express Decembe

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide9. Reset and ClocksThis chapter covers the functional aspects of the reset a

9–2 Chapter 9: Reset and ClocksResetArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 9–1. Reset ControllerExample Desi

Chapter 9: Reset and Clocks 9–3ResetDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 9–2 illustrates the reset sequenc

9–4 Chapter 9: Reset and ClocksClocksArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideAs Figure 9–3 illustrates, the RX trans

Chapter 9: Reset and Clocks 9–5ClocksDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideThe Hard IP contains a clock domain cro

9–6 Chapter 9: Reset and ClocksClocksArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFor designs that transition between Gen

Chapter 9: Reset and Clocks 9–7ClocksDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTransceiver Clock SignalsAs Figure 9–5

9–8 Chapter 9: Reset and ClocksClocksArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide

December 2013 Altera Corporation Arria V Hard IP for PCI Express User Guide10. Transaction Layer Protocol (TLP)DetailsThis chapter provides detailed i

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–3MegaWizard Plug-In Manager Design FlowDecember 2013 Altera Corporation Arria V Ha

10–2 Chapter 10: Transaction Layer Protocol (TLP) DetailsSupported Message TypesArria V Hard IP for PCI Express December 2013 Altera CorporationUser G

Chapter 10: Transaction Layer Protocol (TLP) Details 10–3Transaction Layer Routing RulesDecember 2013 Altera Corporation Arria V Hard IP for PCI Expre

10–4 Chapter 10: Transaction Layer Protocol (TLP) DetailsReceive Buffer ReorderingArria V Hard IP for PCI Express December 2013 Altera CorporationUser

Chapter 10: Transaction Layer Protocol (TLP) Details 10–5Receive Buffer ReorderingDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser

10–6 Chapter 10: Transaction Layer Protocol (TLP) DetailsReceive Buffer ReorderingArria V Hard IP for PCI Express December 2013 Altera CorporationUser

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide11. InterruptsThis chapter describes interrupts for the following configurat

11–2 Chapter 11: InterruptsInterrupts for Endpoints Using the Avalon-ST Application InterfaceArria V Hard IP for PCI Express December 2013 Altera Corp

Chapter 11: Interrupts 11–3Interrupts for Endpoints Using the Avalon-ST Application InterfaceDecember 2013 Altera Corporation Arria V Hard IP for PCI

11–4 Chapter 11: InterruptsInterrupts for Root Ports Using the Avalon-ST Interface to the Application LayerArria V Hard IP for PCI Express December 20

Chapter 11: Interrupts 11–5Interrupts for Endpoints Using the Avalon-MM Interface to the Application LayerDecember 2013 Altera Corporation Arria V Har

© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar

2–4 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressCustomizing the Endpoint in the MegaWizard Plug-In Manager Design FlowArria V Har

11–6 Chapter 11: InterruptsInterrupts for Endpoints Using the Avalon-MM Interface to the Application LayerArria V Hard IP for PCI Express December 201

Chapter 11: Interrupts 11–7Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X SupportDecember 2013 Altera Corporation Arr

11–8 Chapter 11: InterruptsInterrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X SupportArria V Hard IP for PCI Express Dece

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide12. Optional FeaturesThis chapter provides information on several additional

12–2 Chapter 12: Optional FeaturesECRCArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideCvP has the following advantages: Pro

Chapter 12: Optional Features 12–3ECRCDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTable 12–1 summarizes the RX ECRC func

12–4 Chapter 12: Optional FeaturesLane Initialization and ReversalArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideLane Initi

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide13. Flow ControlThroughput analysis requires that you understand the Flow Co

13–2 Chapter 13: Flow ControlThroughput of Posted WritesArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideEach receiver also m

Chapter 13: Flow Control 13–3Throughput of Non-Posted ReadsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide6. After an FC Up

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–5Customizing the Endpoint in the MegaWizard Plug-In Manager Design FlowDecember 20

13–4 Chapter 13: Flow ControlThroughput of Non-Posted ReadsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideNevertheless, mai

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide14. Error HandlingEach PCI Express compliant device must implement a basic l

14–2 Chapter 14: Error HandlingPhysical Layer ErrorsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuidePhysical Layer ErrorsTab

Chapter 14: Error Handling 14–3Transaction Layer ErrorsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTransaction Layer Err

14–4 Chapter 14: Error HandlingTransaction Layer ErrorsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideCompletion timeoutUnc

Chapter 14: Error Handling 14–5Error Reporting and Data PoisoningDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideError Repor

14–6 Chapter 14: Error HandlingUncorrectable and Correctable Error Status BitsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Gui

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide15. Transceiver PHY IP ReconfigurationAs silicon progresses towards smaller

15–2 Chapter 15: Transceiver PHY IP ReconfigurationArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideWhen you instantiate the

Chapter 15: Transceiver PHY IP Reconfiguration 15–3December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 15–3 shows the con

2–6 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressCustomizing the Endpoint in the MegaWizard Plug-In Manager Design FlowArria V Har

15–4 Chapter 15: Transceiver PHY IP ReconfigurationArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide16. SDC Timing ConstraintsYou must include component-level Synopsys Design C

16–2 Chapter 16: SDC Timing ConstraintsSDC Constraints for the Example DesignArria V Hard IP for PCI Express December 2013 Altera CorporationUser Gui

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide17. Testbench and Design ExampleThis chapter introduces the Root Port or End

17–2 Chapter 17: Testbench and Design ExampleEndpoint TestbenchArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide It can only

Chapter 17: Testbench and Design Example 17–3Root Port TestbenchDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide <qsys_s

17–4 Chapter 17: Testbench and Design ExampleChaining DMA Design ExamplesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide1 O

Chapter 17: Testbench and Design Example 17–5Chaining DMA Design ExamplesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideThe

17–6 Chapter 17: Testbench and Design ExampleChaining DMA Design ExamplesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide T

Chapter 17: Testbench and Design Example 17–7Chaining DMA Design ExamplesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideThe

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–7Customizing the Endpoint in the MegaWizard Plug-In Manager Design FlowDecember 20

17–8 Chapter 17: Testbench and Design ExampleChaining DMA Design ExamplesArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideThe

Chapter 17: Testbench and Design Example 17–9Chaining DMA Design ExamplesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide a

17–10 Chapter 17: Testbench and Design ExampleChaining DMA Design ExamplesArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideCh

Chapter 17: Testbench and Design Example 17–11Chaining DMA Design ExamplesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTa

17–12 Chapter 17: Testbench and Design ExampleChaining DMA Design ExamplesArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTa

Chapter 17: Testbench and Design Example 17–13Chaining DMA Design ExamplesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide1

17–14 Chapter 17: Testbench and Design ExampleTest Driver ModuleArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideEach descrip

Chapter 17: Testbench and Design Example 17–15Test Driver ModuleDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide3. If a suit

17–16 Chapter 17: Testbench and Design ExampleTest Driver ModuleArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide2. Sets up t

Chapter 17: Testbench and Design Example 17–17Test Driver ModuleDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideDMA Read Cyc

2–8 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressCustomizing the Endpoint in the MegaWizard Plug-In Manager Design FlowArria V Har

17–18 Chapter 17: Testbench and Design ExampleRoot Port Design ExampleArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide2. Set

Chapter 17: Testbench and Design Example 17–19Root Port Design ExampleDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide Test

17–20 Chapter 17: Testbench and Design ExampleRoot Port BFMArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide altpcietb_bfm_v

Chapter 17: Testbench and Design Example 17–21Root Port BFMDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideThe functionality

17–22 Chapter 17: Testbench and Design ExampleRoot Port BFMArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideBFM Memory Map Th

Chapter 17: Testbench and Design Example 17–23Root Port BFMDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide3. Assigns values

17–24 Chapter 17: Testbench and Design ExampleRoot Port BFMArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideThe ebfm_cfg_rp_e

Chapter 17: Testbench and Design Example 17–25Root Port BFMDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideBesides the ebfm_

17–26 Chapter 17: Testbench and Design ExampleRoot Port BFMArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideIf addr_map_4GB_l

Chapter 17: Testbench and Design Example 17–27Root Port BFMDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 17–7 shows

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–9Qsys Design FlowDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressU

17–28 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide e

Chapter 17: Testbench and Design Example 17–29BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guideeb

17–30 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guideeb

Chapter 17: Testbench and Design Example 17–31BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guideeb

17–32 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guideeb

Chapter 17: Testbench and Design Example 17–33BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guideeb

17–34 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideBF

Chapter 17: Testbench and Design Example 17–35BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guideeb

17–36 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidesh

Chapter 17: Testbench and Design Example 17–37BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidesh

2–10 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressQsys Design FlowArria V Hard IP for PCI Express December 2013 Altera Corporatio

17–38 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideYo

Chapter 17: Testbench and Design Example 17–39BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guideeb

17–40 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guideeb

Chapter 17: Testbench and Design Example 17–41BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidehi

17–42 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidehi

Chapter 17: Testbench and Design Example 17–43BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidedi

17–44 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidedi

Chapter 17: Testbench and Design Example 17–45BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidedm

17–46 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidedm

Chapter 17: Testbench and Design Example 17–47BFM Procedures and FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidems

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–11Qsys Design FlowDecember 2013 Altera Corporation Arria V Hard IP for PCI Express

17–48 Chapter 17: Testbench and Design ExampleBFM Procedures and FunctionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidefi

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide18. DebuggingAs you bring up your PCI Express system, you may face a number

18–2 Chapter 18: DebuggingLink TrainingArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideYou can use SignalTap II Embedded Log

Chapter 18: Debugging 18–3Link TrainingDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideLink fails with the LTSSM toggling be

18–4 Chapter 18: DebuggingLink Hangs in L0 Due To Deassertion of tx_st_readyArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide

Chapter 18: Debugging 18–5Link Hangs in L0 Due To Deassertion of tx_st_readyDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide

18–6 Chapter 18: DebuggingRecommended Reset Sequence to Avoid Link Training IssuesArria V Hard IP for PCI Express December 2013 Altera CorporationUser

Chapter 18: Debugging 18–7Setting Up SimulationDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide1. In the top-level testbench

18–8 Chapter 18: Debugging).Use Third-Party PCIe AnalyzerArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide3. To disable the s

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideA. Transaction Layer Packet (TLP) HeaderFormatsTable A–1 through Table A–9 s

2–12 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressQsys Design FlowArria V Hard IP for PCI Express December 2013 Altera Corporatio

A–2 Chapter :TLP Packet Format without Data PayloadArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTable A–5. Configuration

Chapter : A–3TLP Packet Format with Data PayloadDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTLP Packet Format with Data

A–4 Chapter :TLP Packet Format with Data PayloadArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTable A–15. Completion Lock

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideAdditional InformationThis chapter provides additional information about the

Info–2 Revision HistoryArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideDate Version Changes Made SPRNovember 2013 13.1 Add

How to Contact Altera Info–3December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideHow to Contact AlteraTo locate the most up-to-da

Info–4 Typographic ConventionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTypographic ConventionsThe following table sh

Typographic Conventions Info–5December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidew A warning calls attention to a condition or

Info–6 Typographic ConventionsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–13Qsys Design FlowDecember 2013 Altera Corporation Arria V Hard IP for PCI Express

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideContentsChapter 1. DatasheetFeatures . . . . . . . . . . . . . . . . . . . .

2–14 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressQsys Design FlowArria V Hard IP for PCI Express December 2013 Altera Corporatio

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–15Compiling the Design in the Qsys Design FlowDecember 2013 Altera Corporation Arr

2–16 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressCompiling the Design in the Qsys Design FlowArria V Hard IP for PCI Express Dece

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–17Compiling the Design in the Qsys Design FlowDecember 2013 Altera Corporation Arr

2–18 Chapter 2: Getting Started with the Arria Hard IP for PCI ExpressModifying the Example DesignArria V Hard IP for PCI Express December 2013 Alter

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide3. Getting Started with the Avalon-MMArria Hard IP for PCI ExpressThis Qsys

3–2 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressRunning QsysArria V Hard IP for PCI Express December 2013 Altera Corpor

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–3Customizing the Arria V Hard IP for PCI Express IP CoreDecember 2013 A

3–4 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressCustomizing the Arria V Hard IP for PCI Express IP CoreArria V Hard IP

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–5Adding the Remaining Components to the Qsys SystemDecember 2013 Altera

1–ivArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuidePower Management . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressAdding the Remaining Components to the Qsys SystemArria V Hard IP for P

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–7Adding the Remaining Components to the Qsys SystemDecember 2013 Altera

3–8 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressCompleting the Connections in QsysArria V Hard IP for PCI Express Decem

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–9Specifying Clocks and InterruptsDecember 2013 Altera Corporation Arria

3–10 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressSpecifying Address AssignmentsArria V Hard IP for PCI Express December

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–11Simulating the Example DesignDecember 2013 Altera Corporation Arria V

3–12 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressSimulating the Example DesignArria V Hard IP for PCI Express December

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–13Simulating the Example DesignDecember 2013 Altera Corporation Arria V

3–14 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressSimulating the Example DesignArria V Hard IP for PCI Express December

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–15Simulating the Single DWord DesignDecember 2013 Altera Corporation Arr

1–vDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideChapter 7. IP Core InterfacesArria V Hard IP for PCI Express . . . . .

3–16 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressAdding Synopsis Design ConstraintsArria V Hard IP for PCI Express Dece

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–17Compiling the DesignDecember 2013 Altera Corporation Arria V Hard IP f

3–18 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI ExpressProgramming a DeviceArria V Hard IP for PCI Express December 2013 Alte

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide4. Parameter Settings for the Arria VHard IP for PCI ExpressThis chapter de

4–2 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressSystem SettingsArria V Hard IP for PCI Express December 2013 Altera Corporati

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–3Port FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI Expres

4–4 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressPort FunctionsArria V Hard IP for PCI Express December 2013 Altera Corporatio

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–5Port FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI Expres

4–6 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressPort FunctionsArria V Hard IP for PCI Express December 2013 Altera Corporatio

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–7Port FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI Expres

1–viArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidepclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressPort FunctionsArria V Hard IP for PCI Express December 2013 Altera Corporatio

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–9Port FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI Expres

4–10 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressPort FunctionsArria V Hard IP for PCI Express December 2013 Altera Corporati

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–11Port FunctionsDecember 2013 Altera Corporation Arria V Hard IP for PCI Expre

4–12 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI ExpressPort FunctionsArria V Hard IP for PCI Express December 2013 Altera Corporati

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide5. Parameter Settings for the Avalon-MMArria V Hard IP for PCI ExpressThis

5–2 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI ExpressBase Address RegistersArria V Hard IP for PCI Express December 2013

Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express 5–3Device Identification RegistersDecember 2013 Altera Corporation Arr

5–4 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI ExpressPCI Express/PCI CapabilitiesArria V Hard IP for PCI Express Decembe

Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express 5–5PCI Express/PCI CapabilitiesDecember 2013 Altera Corporation Arria

1–viiDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTest Driver Module . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI ExpressPCI Express/PCI CapabilitiesArria V Hard IP for PCI Express Decembe

Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express 5–7PCI Express/PCI CapabilitiesDecember 2013 Altera Corporation Arria

5–8 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI ExpressPCI Express/PCI CapabilitiesArria V Hard IP for PCI Express Decembe

Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express 5–9Avalon Memory-Mapped System SettingsDecember 2013 Altera Corporatio

5–10 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI ExpressAvalon to PCIe Address Translation SettingsArria V Hard IP for PCI

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide6. IP Core ArchitectureThis chapter describes the architecture of the Arria

6–2 Chapter 6: IP Core ArchitectureArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideAs Figure 6–1 illustrates, an Avalon-ST i

Chapter 6: IP Core Architecture 6–3Key InterfacesDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideKey InterfacesIf you select

6–4 Chapter 6: IP Core ArchitectureKey InterfacesArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidecredits become available. B

Chapter 6: IP Core Architecture 6–5Protocol LayersDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideTransceiver Reconfiguratio

1–viiiArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidedma_set_wr_desc_data Procedure . . . . . . . . . . . . . . . . . . .

6–6 Chapter 6: IP Core ArchitectureProtocol LayersArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideTracing a transaction thro

Chapter 6: IP Core Architecture 6–7Protocol LayersDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide2. The Application Layer r

6–8 Chapter 6: IP Core ArchitectureProtocol LayersArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide Management of the retry

Chapter 6: IP Core Architecture 6–9Protocol LayersDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide Transaction Layer Packet

6–10 Chapter 6: IP Core ArchitectureProtocol LayersArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideFigure 6–5 illustrates th

Chapter 6: IP Core Architecture 6–11Protocol LayersDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide LTSSM—This block implem

6–12 Chapter 6: IP Core ArchitectureMulti-Function SupportArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideMulti-Function Sup

Chapter 6: IP Core Architecture 6–13PCI Express Avalon-MM BridgeDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide Control Re

6–14 Chapter 6: IP Core ArchitectureAvalon-MM Bridge TLPsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideThe bridge has the

Chapter 6: IP Core Architecture 6–15Avalon-MM Bridge TLPsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide The Avalon-MM byt

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide1. DatasheetThis document describes the Altera® Arria® V Hard IP for PCI Exp

6–16 Chapter 6: IP Core ArchitectureAvalon-MM Bridge TLPsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideAs an example, Tabl

Chapter 6: IP Core Architecture 6–17Avalon-MM Bridge TLPsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuidePCI Express-to-Aval

6–18 Chapter 6: IP Core ArchitectureAvalon-MM Bridge TLPsArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide2. System software

Chapter 6: IP Core Architecture 6–19Avalon-MM Bridge TLPsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 6–8 illustra

6–20 Chapter 6: IP Core ArchitectureAvalon-MM Bridge TLPsArria V Hard IP for PCI Express December 2013 Altera CorporationUser GuideThis design is cons

Chapter 6: IP Core Architecture 6–21Avalon-MM Bridge TLPsDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guidespecifies 32-bit or

6–22 Chapter 6: IP Core ArchitectureSingle DWord Completer EndpointArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guide Sp[1:0]—

Chapter 6: IP Core Architecture 6–23Single DWord Completer EndpointDecember 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser GuideFigure 6–

6–24 Chapter 6: IP Core ArchitectureSingle DWord Completer EndpointArria V Hard IP for PCI Express December 2013 Altera CorporationUser Guidef For mor

December 2013 Altera Corporation Arria V Hard IP for PCI ExpressUser Guide7. IP Core InterfacesThis chapter describes the signals that are part of the