Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 3
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Physical Layout of Hard IP In Arria 10 Devices.................................................4-1
Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates..............................................4-4
Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates............................................4-5
Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate...................................... 4-7
64- or 128-Bit Avalon-MM Interface to the Application Layer......................... 5-1
32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals .............................5-3
RX Avalon-MM Master Signals ................................................................................................................5-3
64- or 128-Bit Bursting TX Avalon-MM Slave Signals ..........................................................................5-5
Clock Signals ................................................................................................................................................5-8
Reset...............................................................................................................................................................5-8
Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled .......................................5-10
Hard IP Reconfiguration Interface .........................................................................................................5-11
Physical Layer Interface Signals ..............................................................................................................5-13
Serial Data Signals .........................................................................................................................5-13
PIPE Interface Signals .................................................................................................................. 5-14
Test Signals .................................................................................................................................... 5-19
Registers...............................................................................................................6-1
Correspondence between Configuration Space Registers and the PCIe Specification .....................6-1
Type 0 Configuration Space Registers ..................................................................................................... 6-5
Type 1 Configuration Space Registers ..................................................................................................... 6-6
PCI Express Capability Structures.............................................................................................................6-6
Altera-Defined VSEC Registers................................................................................................................. 6-9
CvP Registers..............................................................................................................................................6-10
64- or 128-Bit Avalon-MM Bridge Register Descriptions .................................................................. 6-13
Avalon-MM to PCI Express Interrupt Registers ......................................................................6-15
Programming Model for Avalon-MM Root Port .................................................................................6-26
Sending a Write TLP .................................................................................................................... 6-27
Sending a Read TLP or Receiving a Non-Posted Completion TLP .......................................6-28
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports ............6-28
Root Port TLP Data Registers ..................................................................................................... 6-29
Uncorrectable Internal Error Mask Register ........................................................................................ 6-31
Uncorrectable Internal Error Status Register ....................................................................................... 6-32
Correctable Internal Error Mask Register .............................................................................................6-33
Correctable Internal Error Status Register ............................................................................................6-34
Arria 10 Reset and Clocks................................................................................... 7-1
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer ....................................7-2
Clocks ........................................................................................................................................................... 7-4
Clock Domains ................................................................................................................................7-4
Clock Summary ...............................................................................................................................7-6
Interrupts for Endpoints ....................................................................................8-1
TOC-3
Altera Corporation
- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
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