Altera CIC MegaCore Function Bedienungsanleitung

CIC IP CoreUser GuideSubscribeSend FeedbackUG-CIC2014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

Figure 2-2: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.UG-CIC2014.12.15DSP Builder Design Flow2-9CIC IP Core Getting StartedA

CIC IP Core Functional Description32014.12.15UG-CICSubscribeSend FeedbackYou can select either a decimation or interpolation CIC filter. A decimation

Variable Rate Change FactorsYou can optionally set minimum and maximum values for the decimator or interpolator rate changefactors and enable the rate

processing chain. This strategy can lead to full utilization of the resources and represents the mostefficient hardware implementation.Figure 3-3: Mul

ContentsAbout The CIC IP Core...1-1Altera DSP IP Core Features...

Figure 3-4: Single Input Multiple Output Architecture with Eight ChannelsThe symbols A, B, C, D, E, F, G, H are demultiplexed into four outputs A, E;

Note: A data width of Bout is required for each integrator and differentiator for no data loss.For an interpolation filter, the gain at each filter st

Hogenauer PruningHogenauer pruning uses truncation in intermediate stages with the retained number of bits decreasingmonotonically from stage to stage

Generally, only equalize the response in the passband, but you can sample further than the passband tofine tune the cascaded response of the filter ch

Parameter Value DescriptionNumber of stages 1 to 12 Specifies the required number of stages.Differential delay 1, 2 Specifies the differential delay i

Parameter Value DescriptionDifferentiator datastorageLogic Element,MemorySelects whether to implement the differentiator datastorage as logic elements

Parameter Name ValueSYMBOLS_PER_BEAT Single input, single output architectures, have onesymbol per beat at the source and the sink. MISOarchitectures

CIC IP Core SignalsTable 3-4: CIC IP Core SignalsSignal DirectionDescriptionav_st_in_data Output In Qsys systems, this Avalon-ST-compliant data bus in

Signal DirectionDescriptionout_endofpacket Output Marks the end of the outgoing result group. If '1', a resultcorresponding to channel N-1 i

The multiple symbols per beat scenario applies to both the sink interface on MISO CIC filters and thesource interface of SIMO CIC filters. All other i

About The CIC IP Core12014.12.15UG-CICSubscribeSend FeedbackThe Altera® CIC IP core implements a cascaded integrator-comb (CIC) filter with data ports

Document Revision History42014.12.15UG-CICSubscribeSend FeedbackCIC IP Core User Guide revision history.Table 4-1:Date Version Changes Made2014.12.15

CIC IP Core Device Family SupportAltera offers the following device support levels for Altera IP cores:• Preliminary support—Altera verifies the IP co

Altera verifies that the current version of the Quartus II software compiles the previous version of each IPcore. Altera does not verify that the Quar

Device Filter Type ALMMemory RegistersfMAX (MHz)M10K M20K Primary SecondaryArria V Interpolator 5Channels 3Interfaces886 27 -- 1,776 17 232.61Arria V

Device Filter Type ALMMemory RegistersfMAX (MHz)M10K M20K Primary SecondaryStratixVDecimator 5Channels 3Interfaces1,891 -- 11 5,562 8 450.05StratixVDe

CIC IP Core Getting Started22014.12.15UG-CICSubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many useful IP core

OpenCore Plus evaluation supports the following two operation modes:• Untethered—run the design containing the licensed IP for a limited time.• Tether