Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 208
- Seite / 212
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Date Version Changes Made
• Removed list of static example designs from Example Designs on
page 1-9. You can derive the list from the installation directory
where example designs are available.
• Removed Migration and TLP Format appendices, and added new
appendix Frequently Asked Questions on page 16-1.
• Reorganized sections in Debugging on page 15-1 and Setting Up
Simulation on page 14-49. Removed Reducing Counter Values for
Serial Simulations section, which is no longer relevant. Default
counter values are automatically set for simulation.
• Updated information in SDC Timing Constraints on page 11-2.
• Fixed minor errors and typos.
2014.12.15 14.1 Made the following changes:
• Revised Root Port programming model description, Receiving a
Completion TLP, to cover read and non-posted completions.
• Added Avalon-MM Testbench and Design Example chapter.
• Added statement that the bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types,
the CvP functionality is in the bottom right block.
• Corrected bit definitions for CvP Status register.
• Updated definition of CVP_NUMCLKS in the CvP Mode Control
register.
• Added definitions for test_in[2], test_in[6], and test_in[7].
• Revised discussion of SDC files to include in Quartus II project.
2014.08.18 14.0 Arria 10
Made the following changes to the Arria 10 Avalon-MM Hard IP for
PCI Express
• Optionally changed the cra_address to 14 bits from 12.
• Added simulation log file, altpcie_monitor_a10_dlhip_tlp_file_
log.log, that is automatically generated in your simulation
directory. To simulate in the Quartus II 14.0 software release, you
must regenerate your IP core to create the supporting monitor file
the generates altpcie_monitor_a10_dlhip_tlp_file_log.log. Refer to
Understanding Simulation Dump File Generation for details.
• Added support for 64-bit addressing, making address translation
unnecessary.
• Removed Channel Placement for PCIe in Arria 10 Devices. Please
contact your Altera sales representative for PLL and channel
usage.
C-2
Revision History for the Avalon-MM Interface
UG-01145_avmm
2015.05.14
Altera Corporation
Additional Information
Send Feedback
- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
Verwandte Produkte und Handbücher für Messgeräte Altera Arria 10 Avalon-MM
(207 Seiten)© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.026 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern