Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 78
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Bits Register Description Reset Value Access
[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_
MODE = 1 and PLD_CORE_READY = 1. The following encodings are
defined:
• 1: Selects internal clock from PMA which is required for CVP_
MODE.
• 0: Selects the clock from soft logic fabric. This setting should
only be used when the fabric is configured in USER_MODE with
a configuration file that connects the correct clock.
To ensure that there is no clock switching during CvP, you should
only change this value when the Hard IP for PCI Express has been
idle for 10 µs and wait 10 µs after changing this value before
resuming activity.
1’b0 RW
[0] CVP_MODE. Controls whether the IP core is in CVP_MODE or normal
mode. The following encodings are defined:
• 1:CVP_MODE is active. Signals to the FPGA control block active
and all TLPs are routed to the Configuration Space. This CVP_
MODE cannot be enabled if CVP_EN = 0.
• 0: The IP core is in normal mode and TLPs are routed to the
FPGA fabric.
1’b0 RW
Table 6-9: CvP Data Registers
The following table defines the CvP Data registers. For 64-bit data, the optional CvP Data2 stores the upper 32
bits of data. Programming software should write the configuration data to these registers. If you Every write to
these register sets the data output to the FPGA control block and generates <n> clock cycles to the FPGA control
block as specified by the CVP_NUM_CLKS field in the CvP Mode Control register. Software must ensure that all bytes
in the memory write dword are enabled. You can access this register using configuration writes, alternatively,
when in CvP mode, these registers can also be written by a memory write to any address defined by a memory
space BAR for this device. Using memory writes should allow for higher throughput than configuration writes.
Bits Register Description Reset Value Access
[31:0] Upper 32 bits of configuration data to be transferred to the FPGA
control block to configure the device. You can choose 32- or 64-
bit data.
0x00000000 RW
[31:0] Lower 32 bits of configuration data to be transferred to the FPGA
control block to configure the device.
0x00000000 RW
Table 6-10: CvP Programming Control Register
This register is written by the programming software to control CvP programming.
Bits Register Description Reset Value Access
[31:2] Reserved. 0x0000 RO
6-12
CvP Registers
UG-01145_avmm
2015.05.14
Altera Corporation
Registers
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- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
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