Altera CPRI v6.0 MegaCore Function Bedienungsanleitung

CPRI v6.0 MegaCore Function User GuideLast updated for Altera Complete Design Suite: 14.0 and 14.0 Arria 10EditionSubscribeSend FeedbackUG-011562015.0

Release InformationTable 1-5: CPRI v6.0 IP Core Current Release InformationItem DescriptionCompatibleQuartus IISoftwareVersion14.0 14.0 Arria 10 Editi

Table 5-13: CPRI v6.0 IP Core START_UP_TIMER Register at Offset 0x28Bits Field Name Type Value onResetDescription31:20 Reserved UR0 12'b019:0 sta

Table 5-15: CPRI v6.0 IP Core CTRL_INDEX Register at Offset 0x30Frequency differences between the control and status interface clock cpu_clk and the m

Table 5-16: CPRI v6.0 IP Core TX_CTRL Register at Offset 0x34Frequency differences between the control and status interface clock cpu_clk and the main

Bits Field Name Type Value onResetDescription7:0 lcv RC 8'b0 Number of line code violations (LCVs) detected in the 8B/10Bdecoding block in the tr

Bits Field Name Type Value onResetDescription10:8 loop_reversedRW 3'b0 Testing reverse loopback mode. If you turn on Enable reverseloopback path

Bits Field Name Type Value onResetDescription1:0 loop_forwardRW 2'b0 Testing forward loopback mode. If you turn on Enabletransceiver PMA forward

Bits Field Name Type Value onResetDescription8 tx_buf_resyncRW 1'b0 Force transmit buffer pointer resynchronization. You can usethis register fie

Bits Field Name Type Value onResetDescription(RX_BUF_DEPTH -1):0rx_buf_delayRO 0 Current receive buffer fill level. Unit is 32-bit words. Maximumvalue

Bits Field Name Type Value onResetDescription23 rx_ex_delay_validRC 1'b0 Indicates that the rx_ex_delay field has been updated.22:RX_BUF_DEPTHRes

Bits Field Name Type Value onResetDescription20:16 rx_bitslip_outRO 5'b0 Number of bits of delay (bitslip) detected at the receiver word-aligner.

OpenCore Plus Time-Out BehaviorOpenCore Plus hardware evaluation can support the following two modes of operation:• Untethered—the design runs for a l

Differences Between CPRI v6.0 IP Core and CPRIIP CoreA2014.08.18UG-01156SubscribeSend FeedbackThe CPRI v6.0 IP core achieves low latency and lower res

Property CPRI v6.0 IP Core (Initial Release) CPRI IP CoreEthernet MAC Includes Ethernet PCS block thatcommunicates with user logicthrough an IEEE 802.

• MegaCore IP Library Release Notes and ErrataFor information about changes in different versions of the legacy CPRI IP core, refer to the ProductRevi

Additional InformationB2015.02.16UG-01156SubscribeSend FeedbackCPRI v6.0 MegaCore Function User Guide Revision HistoryTable B-1: Document Revision His

How to Contact AlteraTable B-2: How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to this table. You can als

Visual Cue MeaningItalic Type with Initial Capital Letters Indicate document titles. For example, Stratix VDesign Guidelines.italic type Indicates va

Getting Started with the CPRI v6.0 IP Core22014.08.18UG-01156SubscribeSend FeedbackExplains how to install, parameterize, and simulate the Altera CPRI

Installation and LicensingThe CPRI v6.0 IP core is an extended IP core which is not included with the Quartus II release. Thissection provides a gener

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 2-3: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

CPRI v6.0 IP Core ParametersThe CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP coreand simulation testbe

Parameter Range DefaultSettingParameter DescriptionReceiver FIFO depth4, 5, 6, 7, or 8 6The value you specify for this parameter is log2 ofthe IP core

ContentsAbout the CPRI v6.0 IP Core...1-1CPRI v6.0 IP Core Supported Featur

Parameter Range DefaultSettingParameter DescriptionAuxiliary latencycycle(s)0 to 9 0Specifies the additional write latency on the AUXTX interface and

Parameter Range DefaultSettingParameter DescriptionEnable direct ctrl_axcaccess interface• On• OffOffTurn on this parameter to include a dedicatedinte

Parameter Range DefaultSettingParameter DescriptionL2 Ethernet PCS Tx/Rx FIFO depth7, 8, 9, 10 7The value you specify for this parameter is log2 ofthe

The CPRI v6.0 IP core requires that you define, instantiate, and connect the following additional softwareand hardware modules for all CPRI v6.0 IP co

Drive the clean-up PLL with the CPRI v6.0 IP core xcvr_recovered_clk output clock, and connect thecleaned up output to the external TX PLL input refer

User logic must provide the connection. Refer to the demonstration testbench for example working userlogic including one correct method to instantiate

You must connect the external reset controller signals and the CPRI v6.0 IP core reset controller interfacesignals according to the following rules. R

Simulating Altera IP CoresThe Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supportedEDA simulators. Simula

Understanding the TestbenchAltera provides a demonstration testbench with the CPRI v6.0 IP core.If you click Example Design in the CPRI v6.0 parameter

Parameter ValueOperation mode MasterSupported receiver CDR frequency (MHz) 307.2Receiver FIFO depth (value shown is log2 of actualdepth)6Enable auto-r

Media Independent Interface (MII) to External Ethernet Block... 3-32CPU Interface to CPRI v6.0 IP

Note: You must select a simulator that is supported by the Quartus II v14.0 or v14.0 Arria 10 Editionsoftware, as appropriate.9. Change directory to y

Functional Description32014.08.18UG-01156SubscribeSend FeedbackThe Altera CPRI v6.0 IP core implements Layer 1 of the CPRI V6.0 specification and prov

Multiple interfaces control the contents of the outbound CPRI frame control words and data. The CPRIv6.0 implements the following transmission priorit

CPRI v6.0 IP Core Clocking StructureFigure 3-2: CPRI v6.0 IP Core Clocking StructureIllustrates the clocks and clock domains in the CPRI v6.0 IP core.

CPRI v6.0 Input Clock Informationcpri_10g_coreclkDrives the CPRI v6.0 IP core clock cpri_clkout when the IP coreis running at the CPRI line bit rate o

CPRI v6.0 IP Core Reset RequirementsTo reset the entire CPRI v6.0 IP core, you must assert the reset signals to the required external resetcontroller

Figure 3-3: Required External BlocksAn example showing how you could connect required components to a single CPRI v6.0 IP core.Reset ControllerReset C

Table 3-4: Start-Up Sequence Interface SignalsAll interface signals are clocked by the cpri_clkout clock.Signal Name Direction Descriptionstate_startu

Signal Name Direction Descriptionnego_protocol_complete InputIndicates the CPRI protocol version negotiation iscomplete.This signal is available only

Figure 3-4: Start-Up Sequence State Machine Timing Diagram000 111 110 101001 011000001011 111 110cpri_clkoutstate_startup_sequencestate_l1_syncnego_bi

TX_EX_DELAY Register...5-18RX_E

AUX Interface SignalsTable 3-5: AUX Interface SignalsIf you turn on Enable auxiliary interface in the CPRI v6.0 parameter editor, the AUX interface is

AUX RX Interface Data SignalsSignal Name Direction Descriptionaux_rx_ctrl[3:0] Output Control slots indicator. Each asserted bit indicates that thecor

AUX TX Interface Data SignalsSignal Name Direction Descriptionaux_tx_data[31:0] Input Data the IP core receives on the AUX TX interface. Thedata is al

Figure 3-5: AUX RX Interface Timing DiagramAUX RX interface behavior in a CPRI v6.0 IP core running at 0.6144 Gbps.4095 003255 1149 02 0 1 2 3 0 1 2X

Figure 3-7: AUX TX Interface Timing Diagram with One Auxiliary Latency CycleExpected behavior on the AUX TX interface of a CPRI v6.0 IP core running a

Figure 3-8: AUX TX Interface Timing Diagram with Four Auxiliary Latency CyclesExpected behavior on the AUX TX interface of a CPRI v6.0 IP core running

Figure 3-9: AUX TX Timing Diagram with ErrorIllustrates the behavior of the aux_tx_err signal on the AUX TX interface of a CPRI v6.0 IP core runningat

AUX Interface SynchronizationFigure 3-10: Relationship Between Synchronization Pulses and Numbers on the AUX InterfaceThe output synchronization signa

In the CPRI v6.0 parameter editor, you can specify a non-zero number of Auxiliary latency cycle(s) toincrease the write latency on the AUX TX interfac

various direct interfaces in this format. The only exception is the L1 CSR interface, which transmits andreceives information in individual bits.Figur

About the CPRI v6.0 IP Core12014.08.18UG-01156SubscribeSend FeedbackThe Altera® CPRI v6.0 MegaCore® function implements the CPRI Specification V6.0 (2

0 1 2 ... 30 31[31:24] #Z.X.0.0(1)#Z.X.0.4(1)#Z.X.1.0 ... #Z.X.14.0 #Z.X.15.4[23:16] #Z.X.0.1(1)#Z.X.0.5(1)#Z.X.1.1

Direct IQ InterfaceIf you turn on Enable direct IQ mapping interface in the CPRI v6.0 parameter editor, the direct IQinterface is available. This inte

Figure 3-14: Direct IQ RX Interface Timing DiagramDirect IQ RX interface behavior in a CPRI v6.0 IP core running at 0.6144 Gbps.The aux_rx_x and aux_r

Related InformationAvalon Interface SpecificationsFor more information about the Avalon-ST protocol, including timing diagrams, refer to the AvalonStr

Figure 3-16: Direct VS RX Timing DiagramDirect VS RX interface behavior in a CPRI v6.0 IP core running at 0.6144 Gbps.The aux_rx_x signal is not part

Figure 3-17: Direct VS TX Timing DiagramExpected behavior on the direct VS TX interface of a CPRI v6.0 IP core running at 0.6144 Gbps.The aux_tx_x sig

Table 3-8: Real-Time Vendor Specific Interface SignalsAll interface signals are clocked by the cpri_clkout clock.Real-Time Vendor Specific RX Interfac

Figure 3-19: Direct RTVS TX Timing DiagramExpected behavior on the direct RTVS TX interface of a CPRI v6.0 IP core running at 10.1376 Gbps.The aux_tx_

Direct HDLC Serial RX InterfaceSignal Name Direction Descriptionhdlc_rx_data Output HDLC data stream received from the CPRI frame. Thehdlc_rx_valid si

Direct L1 Control and Status InterfaceIf you turn on Enable Z.130.0 access interface in the CPRI v6.0 parameter editor, the direct L1 controland statu

CPRI v6.0 IP Core Supported FeaturesThe CPRI v6.0 IP core offers the following features:• Compliant with the Common Public Radio Interface (CPRI) Spec

Signal Name Direction Descriptionz130_local_rai Output Indicates that either the z130_local_lof or the z130_local_los signal is high; clears when both

Figure 3-22: sdi_assert to sdi_req on Direct L1 Control and Status Interfacecpri_clkoutMaster z130_sdi_assertDL Frame Z.130.0[2] (Internal)Slave z130_

Figure 3-24: LOF, LOS, and RAI on Direct L1 Control and Status Interfacecpri_clkoutz130_local/remote_lofz130_local/remote_losz130_local/remote_raiLOF

RX MII SignalsSignal Name Direction Descriptionmii_rxreset Input Resets the MII receiver interface and FIFO read logic. Thisreset signal is active low

MII Status SignalsSignal Name Direction Descriptionmii_tx_fifo_status[3:0] Output Ethernet Tx PCS FIFO fill level status. The individual bitshave the

Figure 3-26: TX MII Timing Diagrammii_txclkmii_txenmii_txdmii_txerEncoded FrameD1 D2 D3 D4 D5 D6 D7 XX/J/ /K/ /D1/ /D2/ /F/ /D4/ /F/ X/I/ /D6/ /D7/ /T

CPU Interface SignalsTable 3-12: CPRI v6.0 IP Core CPU Interface SignalsThe CPRI v6.0 IP core CPU interface has the following features:• Avalon-MM sla

Accessing the Hyperframe Control WordsWhen you turn on Enable all control word access in the CPRI v6.0 parameter editor, you can access the256 control

Specifying the Position in the Control WordYou can access only 32 bits in a single register access. Depending on the CPRI line bit rate, a control wor

Example 3-1: Control Word Retrieval ExampleTo retrieve the vendor-specific portion of a control word in the most recent received hyperframe,perform th

CPRI v6.0 IP Core Device Family and Speed Grade SupportThe following sections list the device family and device speed grade support offered by the CPR

6. If the CPRI line bit rate is greater than 6.144 Gbps, increment the tx_ctrl_seq field of theCTRL_INDEX register to the value of 3 and write the fou

Table 3-14: Auto-Rate Negotiation Control and Status Interface SignalsAll interface signals are clocked by the cpri_clkout clock.Signal Name Direction

sections explain how you set and use these register values to derive the extended Tx delay measurementinformation.M/N Ratio SelectionAs your selected

calculate the number of cpri_clkout clock cycles of delay through the Rx buffer directly, asrx_msrm_period/N.Related Information• TX_EX_DELAY Register

Table 3-18: Delays on Transmit Path Through CPRI v6.0 IP Core in Arria 10 DevicesIn this table, P1 is the duration of one cpri_clkout clock cycle, and

Table 3-21: Delays on Receive Path Through CPRI v6.0 IP Core in Stratix V DevicesIn this table, P1 is the duration of one cpri_clkout clock cycle, and

Main Transceiver Clock and Reset SignalsTable 3-23: Main Transceiver Clock and Reset-Done SignalsThe clocks for individual interfaces are listed with

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an Avalonmaster to this bus to access the registers of the embed

Signal Name Direction Descriptionxcvr_tx_cal_busyOutput Indicates to external reset controller that the transmitter isstill busy with the calibration

Transceiver Debug InterfaceTable 3-28: Transceiver Debug Interface SignalsIf you turn on Enable debug interface in the CPRI v6.0 parameter editor, the

CPRI v6.0 IP Core Performance: Device Speed Grade SupportTable 1-3: Slowest Supported Device Speed GradesLower speed grade numbers correspond to faste

Table 3-29: Loopback ModesTag in Figure Description How to Configure1 External loopback: Use this configurationto test the full Tx and Rx paths from a

Related InformationL1_CONFIG Register on page 5-4UG-011562014.08.18CPRI v6.0 IP Core Self-Synchronization Feature3-51Functional DescriptionAltera Corp

CPRI v6.0 IP Core Signals42014.08.18UG-01156SubscribeSend FeedbackThe CPRI v6.0 IP core communicates with the surrounding design through multiple exte

Signal Name Direction Interfacemii_tx_fifo_status[3:0] OutputMII status signalsThese signals are available only if you turn on EnableIEEE 802.3 100BAS

Signal Name Direction Descriptionaux_tx_data[31:0] InputAUX TX interface data signalsThese signals are available only if you turn on Enableauxiliary i

Signal Name Direction Descriptionhdlc_rx_valid Output Direct HDLC serial RX interfaceThese signals are available only if you turn on Enabledirect HDLC

Table 4-3: CPRI v6.0 IP Core Management SignalsClock NameDirectionDescriptioncpri_clkout OutputMain clock signalscpri_10g_coreclk Inputreset Input Mai

Clock NameDirectionDescriptionex_delay_clk InputExtended delay measurement interfaceex_delay_reset Inputrx_lcv Output L1 debug interfaceThese signals

Signal Name Direction Descriptionreconfig_clk InputArria V GZ and Stratix V transceiver reconfigurationinterfaceThese signals are present only in P co

Related Information• Main Transceiver Clock and Reset Signals on page 3-46• CPRI Link on page 3-45• Arria V GZ and Stratix V Transceiver Reconfigurati

Table 1-4: IP Core FPGA Resource UtilizationLists the resources and expected performance for selected variations of the CPRI v6.0 IP core in an Arria

CPRI v6.0 IP Core Registers52015.02.16UG-01156SubscribeSend FeedbackThe CPRI v6.0 IP core internal registers are accessible using the CPU interface, a

Offset Register Name Function Location of Additional Information0x14 TX_SCR Transmitter ScramblerControlTX_SCR Register on page 5-70x18 RX_SCR Receive

INTR RegisterTable 5-3: CPRI v6.0 IP Core INTR Register at Offset 0x00Bits Field Name Type Value onResetDescription31:19 Reserved UR0 13'b018 int

Bits Field Name Type Value onResetDescription11 rx_freq_alarm_holdRC 1'b0 CPRI receive clock is not synchronous with main IP core clock(cpri_clko

Bits Field Name Type Value onResetDescription2 tx_enable_forceRW 1'b0 Specifies whether the RE slave self-synchronization testingfeature is activ

Bits Field Name Type Value onResetDescription4:0 bit_rate #nik1411442180153/fn_RO_or_RW#nik1411442180153/fn_param_ed_detCPRI line bit rate to be used

Bits Field Name Type Value onResetDescription9prot_ver_autoRW 1'b1 Enables auto negotiation of protocol version.If you turn on Enable L1 inband p

Table 5-9: CPRI v6.0 IP Core RX_SCR Register at Offset 0x18Bits Field Name Type Value onResetDescription31 rx_scr_activeRO 1'b0 Indicates that th

CM_STATUS RegisterTable 5-11: CPRI v6.0 IP Core CM_STATUS Register at Offset 0x20Bits Field Name Type Value onResetDescription31:12 Reserved UR0 20&ap

Bits Field Name Type Value onResetDescription10:8 state_startup_seqRO 3'b0 Indicates the current state of the start-up sequence. This fieldhas th