Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 167
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The ebfm_cfg_rp_ep executes the following steps to initialize the Configuration Space:
1. Sets the Root Port Configuration Space to enable the Root Port to send transactions on the PCI
Express link.
2. Sets the Root Port and Endpoint PCI Express Capability Device Control registers as follows:
a. Disables Error Reporting in both the Root Port and Endpoint. BFM does not have error handling
capability.
b. Enables Relaxed Ordering in both Root Port and Endpoint.
c. Enables Extended Tags for the Endpoint, if the Endpoint has that capability.
d. Disables Phantom Functions, Aux Power PM, and No Snoop in both the Root Port and Endpoint.
e. Sets the Max Payload Size to what the Endpoint supports because the Root Port supports the
maximum payload size.
f. Sets the Root Port Max Read Request Size to 4 KBytes because the example Endpoint design
supports breaking the read into as many completions as necessary.
g. Sets the Endpoint Max Read Request Size equal to the Max Payload Size because the Root Port
does not support breaking the read request into multiple completions.
3. Assigns values to all the Endpoint BAR registers. The BAR addresses are assigned by the algorithm
outlined below.
a. I/O BARs are assigned smallest to largest starting just above the ending address of BFM shared
memory in I/O space and continuing as needed throughout a full 32-bit I/O space.
b. The 32-bit non-prefetchable memory BARs are assigned smallest to largest, starting just above the
ending address of BFM shared memory in memory space and continuing as needed throughout a
full 32-bit memory space.
c. Assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS are based on the value
of the addr_map_4GB_limit input to the ebfm_cfg_rp_ep. The default value of the
addr_map_4GB_limit is 0.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the 32-bit prefetchable
memory BARs are assigned largest to smallest, starting at the top of 32-bit memory space and
continuing as needed down to the ending address of the last 32-bit non-prefetchable BAR.
However, if the addr_map_4GB_limit input is set to 1, the address map is limited to 4 GByte, the
32-bit and 64-bit prefetchable memory BARs are assigned largest to smallest, starting at the top of
the 32-bit memory space and continuing as needed down to the ending address of the last 32-bit
non-prefetchable BAR.
d. If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the 64-bit prefetchable
memory BARs are assigned smallest to largest starting at the 4 GByte address assigning memory
ascending above the 4 GByte limit throughout the full 64-bit memory space.
If the addr_map_4 GB_limit input to the ebfm_cfg_rp_ep is set to 1, then the 32-bit and the 64-bit
prefetchable memory BARs are assigned largest to smallest starting at the 4 GByte address and
assigning memory by descending below the 4 GByte address to addresses memory as needed down
to the ending address of the last 32-bit non-prefetchable BAR.
The above algorithm cannot always assign values to all BARs when there are a few very large (1
GByte or greater) 32-bit BARs. Although assigning addresses to all BARs may be possible, a more
complex algorithm would be required to effectively assign these addresses. However, such a
UG-01145_avmm
2015.05.14
Configuration of Root Port and Endpoint
14-17
Avalon-MM Testbench and Design Example
Altera Corporation
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- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
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