Altera Arria 10 Avalon-MM Bedienungsanleitung Seite 5
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Optional Features..............................................................................................13-1
Configuration via Protocol (CvP) .......................................................................................................... 13-1
ECRC ..........................................................................................................................................................13-2
ECRC on the RX Path .................................................................................................................. 13-2
ECRC on the TX Path .................................................................................................................. 13-3
Avalon-MM Testbench and Design Example .................................................. 14-1
Arria 10 Avalon-MM Endpoint Testbench ...........................................................................................14-2
Arria 10 Avalon-MM Root Port Testbench ..........................................................................................14-4
Endpoint Design Example........................................................................................................................14-4
BAR/Address Map ........................................................................................................................14-6
Avalon-MM Test Driver Module ........................................................................................................... 14-7
DMA Write Cycles ................................................................................................................................... 14-8
DMA Read Cycles ...................................................................................................................................14-10
Avalon-MM Root Port Design Example .............................................................................................14-12
Root Port BFM ........................................................................................................................................14-14
BFM Memory Map .....................................................................................................................14-16
Configuration Space Bus and Device Numbering ................................................................. 14-16
Configuration of Root Port and Endpoint ..............................................................................14-16
Issuing Read and Write Transactions to the Application Layer .......................................... 14-21
BFM Procedures and Functions ........................................................................................................... 14-22
ebfm_barwr Procedure .............................................................................................................. 14-22
ebfm_barwr_imm Procedure ....................................................................................................14-23
ebfm_barrd_wait Procedure ..................................................................................................... 14-24
ebfm_barrd_nowt Procedure ....................................................................................................14-25
ebfm_cfgwr_imm_wait Procedure ...........................................................................................14-26
ebfm_cfgwr_imm_nowt Procedure ......................................................................................... 14-26
ebfm_cfgrd_wait Procedure ......................................................................................................14-27
ebfm_cfgrd_nowt Procedure .....................................................................................................14-28
BFM Configuration Procedures................................................................................................ 14-29
BFM Shared Memory Access Procedures ............................................................................... 14-31
BFM Log and Message Procedures .......................................................................................... 14-34
Verilog HDL Formatting Functions ........................................................................................ 14-38
Procedures and Functions Specific to the Chaining DMA Design Example......................14-42
Setting Up Simulation.............................................................................................................................14-49
Changing Between Serial and PIPE Simulation ..................................................................... 14-49
Using the PIPE Interface for Gen1 and Gen2 Variants .........................................................14-49
Viewing the Important PIPE Interface Signals........................................................................14-49
Disabling the Scrambler for Gen1 and Gen2 Simulations ....................................................14-49
Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations.....................14-50
Debugging .........................................................................................................15-1
Simulation Fails To Progress Beyond Polling.Active State..................................................................15-1
Hardware Bring-Up Issues ......................................................................................................................15-1
Link Training .............................................................................................................................................15-2
TOC-5
Altera Corporation
- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
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