Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 219)

Running the Testbench for Two Avalon-MM Masters Slaves

1. Unzip ug_avalon_verification.zip to a working directory.

2. Open <working_dir>/avlm_avls_2x2.qsys.

3. Complete the following steps to generate the testbench:

a. On the Generate menu, select Generate HDL.

b. Specify the parameters shown in the following table:

Table 17-4: Generation Parameters

ValueParameter

Synthesis

Leave this option offCreate HDL design files for synthesis

Leave this option offCreate timing and resource estimates for third-party

EDA synthesis tools

Leave this option onCreate block symbol file (.bsf)

Simulation

VHDLCreate simulation model

Leave this option offAllow mixed-language simulation

Output Directory

<working_dir>/avlm_avls_2x2Path

c. Click Generate.

The Qsys Generate window displays informational messages as it generates the testbench.

d. Close the Generate window.

4. Start the ModelSim simulator.

5. To run the simulation, type the following command in your working directory:

do run_simulation.tcl

This command compiles all the required HDL files, elaborates, and runs the simulation.

Altera Corporation

Avalon-MM Verilog HDL and VHDL Testbenches

Send Feedback

17-9

Running the Testbench for Two Avalon-MM Masters Slaves

1 2 ... 214 215 216 217 218 219 220 221 222 223 224

Keine Kommentare

Altera Avalon Verification IP Suite Bedienungsanleitung Seite 219