Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 108)

init()

init()Prototype:

Verilog HDL: None

VHDL: bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Initializes the counters and clears the queue.Description:

Verilog HDL, VHDLLanguage support:

pop_command()

pop_command()Prototype:

Verilog HDL: None

VHDL: bfm_id, req_if(bfm_id)

Arguments:

VoidReturns:

Removes the command descriptor from the queue so that the testbench can

query it with the get_command methods.

Description:

Verilog HDL, VHDLLanguage support:

pop_response()

void pop_response()Prototype:

Verilog HDL: None

VHDL: bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Removes the transaction descriptor from the queue so that the testbench

can query it with the get_command methods. Sequence counter is initialized

to 1.

Description:

Verilog HDL, VHDLLanguage support:

Avalon-MM Monitor

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init()

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