Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 104)

get_response_data()

bit [AV_DATA_W-1:0] get_response_data(int index)Prototype:

Verilog HDL: index

VHDL: response_data, index, bfm_id, req_if(bfm_id)

Arguments:

bit[AV_DATA_W-1:0]Returns:

Returns the transaction read data in the response descriptor that was removed

from the response queue. Each cycle in a burst response is addressed

individually by the specified index. In the case of read responses, the data is

the data captured on the avm_readdata interface pin. In the case of write

responses, the data on the driven avm_writedata pin is captured and

reflected here.

Description:

Verilog HDL, VHDLLanguage support:

get_response_latency()

int get_response_latency(int index)Prototype:

Verilog HDL: index

VHDL: response_latency, index, bfm_id, req_if(bfm_id)

Arguments:

intReturns:

Returns the transaction read latency in the response descriptor that has been

removed from the response queue. Each cycle in a burst read has its own

latency entry.

Description:

Verilog HDL, VHDLLanguage support:

get_response_queue_size()

int get_response_queue_size()Prototype:

Verilog HDL: None

VHDL: response_queue_size, bfm_id, req_if(bfm_id)

Arguments:

automatic intReturns:

Queries the response queue to determine number of response descriptors

currently stored in the BFM. This is the number of responses the test program

can immediately remove from the response queue for further processing.

Description:

Verilog HDL, VHDLLanguage support:

Avalon-MM Monitor

Altera Corporation

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Altera Avalon Verification IP Suite Bedienungsanleitung Seite 104