
3
Reset Source BFM
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The Avalon Verification IP Suite includes a Reset Source BFM that you can use to generate a reset signal in
your testbench.
Parameters
Table 3-1: Reset Source BFM Parameter Settings
DescriptionLegal ValuesDefault ValueOption
Specifies the polarity of the reset signal. Turn on
this option to set the reset signal active high.
On/OffOnAssert reset high
Specifies the number of cycles that the reset signal
is asserted at the initial stage of the simulation.
N/A0Cycles of initial
reset
Reset Source API
reset_assert
reset_assertPrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void.Returns:
Asserts the reset signal.Description:
Verilog HDLLanguage support:
ISO
9001:2008
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